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TI Home » TI E2E Community » Support Forums » Power Management » LED Drivers/LCD Bias » LED Drivers/LCD Bias Forum » Max length of TLC5940 chain?
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Max length of TLC5940 chain?

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Nikhil Dixit
Posted by Nikhil Dixit
on Jan 20 2012 12:36 PM
Prodigy10 points

Hi.

I was wondering what the maximum length is for daisy chaining TLC5940, and what the limiters are. Are lengths around 60 excessive to handle with an Arduino Uno?

Thanks

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  • Brigitte
    Posted by Brigitte
    on Jan 23 2012 02:22 AM
    Suggested Answer
    Genius14085 points

    Hello Nikhil,

    There are several limiting factors with daisy chaining TLC5940 and all of these depend on the application and setup, therefore it is almost impossible to answer correctly where the limit is. Here some limiting factors:

    - The clock signals are sent to the TLC5940 in parallel and the data signals are in series from IC to IC. The data signal is therefore a little bit delayed from one IC to the next one and therefore the clock signals arrive earlier the later the part is in the chain.

    - The clock signal as well is changing over the long distance from the 1st TLC5940 to the last TLC5940. The slope will get flatter.

    The above issues are dependent on the data speed you are using as well as on the distance between the parts. Normally you should be able to overcome both issues with a clock repeater.

    - You need to make sure that there is almost no GND shift from the processor to the last TLC5940, otherwise the communication will fail.

    - You need to make sure that the communication speed is high enough to update all TLC5940 within the data update rate you want to achieve.

    Best regards,
    Brigitte

    daisy chain TLC5940
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  • Michael Borkowski
    Posted by Michael Borkowski
    on Apr 12 2012 06:32 AM
    Prodigy10 points

    Brigitte

    - The clock signals are sent to the TLC5940 in parallel and the data signals are in series from IC to IC. The data signal is therefore a little bit delayed from one IC to the next one and therefore the clock signals arrive earlier the later the part is in the chain.

    Really? If the clock signal arrives, all the TLC parts shift their data bits to the next part (shift in from SIN and shift out to SOUT). The minimum hold time for SIN during a high SCLK is 3 ns, and the maximum propagation time from rise of SCLK to change of SOUT is 30 ns. So when a SCLK pulse arrives at the TLCs in parallel, all TLCs sample their SIN and change their SOUT at the same time. As far as I understand, this means that even at the end of the chain, the data should be shifted correctly; did I misunderstand something?

    Best regards,
    Michael 

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  • MPope
    Posted by MPope
    on Apr 12 2012 16:03 PM
    Verified Answer
    Verified by Brigitte
    Intellectual345 points

    There are really a few facts not in evidence here.

    How many clk drivers and/or their drive strength, size of the pcb, impedance & capacitance of the trace. How is the clk signal routed. Are there any stubs, etc..?

    Speed of a signal on FR4 is ~165ns / in or ~ 6" / ns. clk -> out = 30ns = ~15ft. So propagation speed should not really an issue. Drive strength and signal integrity are going to get you.

    If you could get all of the clks to the pins at the same time - there would be no issue - in theory, but that also would require an elaborate clocking scheme.

    Ground consistency/drop can be a huge issue on something like this where you go over distance. Just try not having your cpu & the leds/5940s not at the same ground potential and see how far you get. If you need those separated, you'll need some isolated drivers - lvds or something like that doesn't need a ground reference. TI has a part that has differential drivers built in - but I don't remember which one - I'm sure someone will chime in or shouldn't be too hard to search for it.

    If you're doing some kind of strip lighting where you want really long distances, just throw in a buffer every 2-3 feet, probably no more than 6'.

    What's a 'hc244 going to cost you $0.10 in 100's.

    If you are doing a matrix - you should probably consider scanning and multiple paths/channels.

    So, with some careful planning - there really shouldn't be a practical limit - save your update rate 12bits * 16outputs per chip * n chips... @ <=30Mhz. So 192 bits * 33.3ns = 6.4us per chip. That goes into your refresh rate x times - for 30 Hz -> 5208 chips (83328 LEDs) - now that's a long chain.

    I say signal integrity again - how long can you keep that clean - a few buffers and some termination can be your friends. Watch your grounding too.

    Have fun designing

    Matt

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  • Brigitte
    Posted by Brigitte
    on Apr 13 2012 03:26 AM
    Genius14085 points

    Hello Matt,

    Are you possibly speaking about the dual LVDS transmitter SN65LVDS9638?

    Best regards,
    Brigitte

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  • MPope
    Posted by MPope
    on Apr 13 2012 09:25 AM
    Intellectual345 points

    I would think something like that should be workable. I'm currently messing around with the 65lvds390 & 391.

    I looked up the other part I was thinking about: TLC5970. There may be others too.

    Hope this helps - Matt

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