We are having problems with cascading TLC5941's. We have 16 cascaded, but partway down the line they start getting incorrect data. This appears to be due to skewing of the clock pulse (which is just bussed to every part as shown in the data sheet). It doesn't take much distortion of the clock before the chip clocks in the previous data bit state rather than the one which has just shifted out. It looks like you really need to buffer the clock for each 1 or 2 devices but I can't see any reference to this anywhere. Is there a recommendation for clock distribution on these devices The clock is about 1MHz but it makes no difference what the speed is, it is down to how fast the clock edge rises.
We are having problems with cascading TLC5941's. We have 16 cascaded, but partway down the line they start getting incorrect data. This appears to be due to skewing of the clock pulse (which is just bussed to every part as shown in the data sheet). It doesn't take much distortion of the clock before the chip clocks in the previous data bit state rather than the one which has just shifted out.
It looks like you really need to buffer the clock for each 1 or 2 devices but I can't see any reference to this anywhere. Is there a recommendation for clock distribution on these devices
The clock is about 1MHz but it makes no difference what the speed is, it is down to how fast the clock edge rises.
Whilst displaying Frame N (a PWM cycle), you can clock in Frame N+1 data. After Frame N is complete, pull BLANK high and toggle XLAT from low to high and then high to low. This will latch the new N+1 data into the internal registers. TLC5946 datasheet, Figure 31 provides an example of this timing. The figure shows the 192 bit dot correction data entry (16 channels * 6 bit dot correction * 2 ICs). It then shows the 384 bit grayscale data entry (16 channels * 12 bit grayscale * 2 ICs). After this frame is latched into the IC, the grayscale clock starts. While the grayscale clock (GSCLK) is running, the next frame of 384 bit grayscale data is entered. Note that this data can not be latched until after the grayscale completes it's 4096 steps and BLANK is pulled high. The only "off" time you should have is when the BLANK signal is pulled high.
You must be careful to ensure the TLC5941 setup and hold requirements are met. If your signal drive strength is too low, the signal edges will be rounded due to the board capacitance on the data and clock lines. There is no requirement to buffer the clock or any other signals. However, depending on your specific drive strengths, board capacitances, clock speeds, timing between signals, you may need to buffer your signals to meet the TLC5941 timing requirements. If you are at the limits of the setup and hold requirements and have rounded edges on your clock and data signals, you might be able to shift the timing between your signals to resolve the problem. It may require a buffer.