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TLC5951 | A few questions

Other Parts Discussed in Thread: TLC5951

I have a couple of questions regarding the TLC5951’s Auto display repeat mode and the timing reset mode.

If I put a message up by setting XBLINK high after XLAT goes high then set Auto display=1, do I not have to change the state of XBLINK until I want to write a different message?  The GS counters don’t reset since XBLINK does not go low so I do not have to rewrite the GS data? Does Display timing reset mode only determine if GSLAT or XBLINK reset the GS counters?

 Thanks and best regards, Steve, TI-AFA Colorado

  • If I put a message up by setting XBLINK high after XLAT goes high then set Auto display=1, do I not have to change the state of XBLINK until I want to write a different message?

    Yes this is correct, you do not need to change toggle XBLINK signal to reste the graysclae counter. In auto repead mode the grayscale counter is reset automatically and the complete garyscale cycle is repeated until you disable the auto repead mode or pul XBLINK low to turn off the outputs

    The GS counters don’t reset since XBLINK does not go low so I do not have to rewrite the GS data?

    Yes the grayscale counters reset automatically, in auto repeat mode you do not need to reset the grayscale counters wit XBLNK signal.

    Anyway you do not need to write new grayscale data since one grayscale cycle is repeated. In case you write new garyscale data it depends if the display reste timing is enabled or disabled.

    If display timing reset is disabled you should pull XBLNK high after a full gaysclae cycle before you latch new garysclae data in with GSLAT.

    If dispaly timing reset is enabled, you can connect XBLNK to VCC, and simple latch new gartsclae data with GSLAT.

    Does Display timing reset mode only determine if GSLAT or XBLINK reset the GS counters?

    When display timing reset is enables the XBLNK can be connected to VCC (it is not needed). If display timing reset is enabled all outputs are forced off and the grayscale counters are restet to zero with rising edge of GSLAT. A new PWM gryascale cycle starts with the next rising edge of GSCKR/G/B