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DDR3 VTT avg current analysis supporting use of LDO
There is an older 3-page App note (AN-1254) from National on DDR Termination using an LDO solution such as the LP2995 instead of a switcher for VTT.
The underlying analysis showing how the current was calculated is the basis for the article, and is referred to on the second page, but is not included in the App Note.
Is there another App Note that dives deeper into these calculations? Of particular interest is how things such as memory bus turn around and latency were considered and if there was statistical analysis around all zeros or all ones for a pattern? And also how cancellation from complementary signals was analyzed, say you had balanced zeros and ones, what did that look like?
Here's the link to the app note: http://www.ti.com/lit/an/snva060/snva060.pdf
I stumbled upon a pretty good article by TI's Peter Miller at: http://www.eetimes.com/design/memory-design/4216279/Powering-DDR-memory-and-SSTL-logic
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