I'm trying to use the TPS7A7300 simulation model in Cadence PSPICE 16.5 (with the AMS simulator option) and I'm running into a few issues. When setting the model to an output voltage other than the simulation default using the pin selection method it appears I cannot set the device below ~1.2V. Additionally, I attempted to apply a dynamic load (current step load) to the output of the supply and the output voltage changes dramatically (~200mV) for the duration of the step -- essentially mirrors the shape of the current instead of having a leading and trailing transient. Are you aware of any issues with this model?
I have just tested the model using the ground taps. If you remove them all, you get 0.5V. When adding each tap, the resulting voltage was increased by the proper amount. Can you provide your schematic or a .zip file of the PSpice directory you are using?
I am not running PSpice 16.5, however. I am using version 16.2.
The LDO model used is a very simple behavioral model that may not represent the transient changes in the load properly. It will change when the load changes, however, the resulting waveform may not be completely accurate. As with any model, this is one of the many trade-offs we made when choosing what kind of model to represent the LDO behavior.
Please see the attached .zip of the working directory. 7416.TPS7A7300_PSPICE_TRANS.zip
The changes I've made to the base simulation are changing the input voltage to 1.5V, changing the taps to 1.0V, and adding a pulsing current load.
My intention for the simulation was to get a feel for the dynamic characteristics of the converter with significant load capacitance at the output (not yet added). Given the information above that this is mainly a behavioral model, would you be able to provide information about the internal error amplifier GBW product / control loop compensation components to allow for modeling of the control system? I'm assuming it might not be worth any time investigating my issue running the model if it appears to not contain the frequency dependent characteristics I'm looking to simulate.
I do not have access to the information you would need for that kind of modeling. The best source would be the design team. You are correct in that the model would not contain this information in the detail you are needing.
Mostly these new LDOs have multiple loops and defy this type modeling - yet I have asked for the information you have requested. No promises, but maybe the system engineer can give us some general guidelines on what you ask.
How much load/output capacitance and esr do you need/want?
Thanks, this is all good info.
Here's what I'm trying to validate through simulation:
1. The input to this converter is from a high current 1.5V switching regulator with a large amount of ceramic capacitance on it's output (this converters input) in the neighborhood of 1000uF.
2. This converter is powering sensitive high speed transceivers that require 1.0V with around a maximum voltage deviation of 10mV peak when going from idle to full load (say 100mA load to 2A).
3. I would estimate I need in excess of 220uF of capacitance on the output of this converter, this is from extrapolating the waveforms provided in the datasheet -- I'm just not sure if I can say 10x the capacitance gets me to 10x lower disturbance on the output.
I realized I didn't answer your question on ESR. The bulk ceramics I'm looking at have an ESR around 3 milli-ohms each, at the resonant frequency the ESR could be as low as 750 u-ohms + board effects, so I would say single digit m-ohms are possible. There will be significant decoupling of this supply up to reasonably high frequencies (total impedance under 100 m-ohms up to around 100 MHz).
The other day we used the TPS7A7300 (basically the same part) to step from 2mA-3Amps at 1V OUT using a feed forward capacitor of 2nF from VOUT to FB and Cout=100uF. The transient peak (dip) was 48mV. A 1% transient - particularly at 1Vout - is very tough. (This was for a 1us/Amp step in load current)
This will take some experimentation on your part - but my only other suggestion is to try the TPS74401, which is slightly faster with better phase margin. Even here you will need a large amount of output capacitance, and a feed forward capacitor across the upper feedback resistor (to shunt the transient directly to the error amp)(1-2nF is usually good for this).
You might be successful if your transient step is much slower than 1us/amp.
Also - you should get an Evaluation Module (EVM) for each LDO from the TI website for experimentation. This is really the only good way I have found to verify that this can be done.
Thanks for the feedback, I'm going to go ahead and try to prove this out experimentally as per your suggestion. Thank you for the feedforward cap recommendation.
All content and materials on this site are provided "as is". TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with regard to these materials, including but not limited to all implied warranties and conditions of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with respect to these materials. No license, either express or implied, by estoppel or otherwise, is granted by TI. Use of the information on this site may require a license from a third party, or a license from TI.
TI is a global semiconductor design and manufacturing company. Innovate with 100,000+ analog ICs andembedded processors, along with software, tools and the industry’s largest sales/support staff.