Trying to find out information on how current limiting is implemented in CMOS LDO regulators but so far failling miserably.
Any information on the subject would be welcome.
There are several different implementations around. The most common is to sense the current through the pass fet using a current mirror. When the current exceeds a preset value, then the drive to the gate of the pass transistor is modulated so that the pass fet becomes a constant current source to the output. The output current will be constant so any increase in the load will decrease the output voltage so the LDO output is essentially power limited to within the safe operataing range of the fet.
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