LP38500 － Board layout for best thermal resistance for exposed package

Hirotaka Matsumoto

Hi All,

Would you mind if we ask LP38500?

<Question>
Our cusotmer will use LP38500ASDX-ADJ/NOPB.
Our cusotmer will design the board with LP38500ASDX-ADJ/NOPB following conditon;

-Condition-
Copper foil：20～25um
GND plane：3 layers( there are three GND plane in the board. Total layers are 8.)

In order to below θj-a=30℃/W, how much of radiation surface area are required on the board?
And, how many of vias are required on the board?
Or, do you have any reference document?
Could you teach us above?

Kind regards,

Hirotaka Matsumoto

over 10 years ago

0 Donald Jones over 9 years ago

TI__Mastermind 22610 points

Please refer to the TI Thermal web page:

www.ti.com/thermal

“Designing for Thermal Performance”

Alternately, a good reference document would be:

“AN-2020 Thermal Design By Insight, Not Hindsight (Rev. C)”

www.ti.com/lit/an/snva419c/snva419c.pdf

0 Donald Jones over 9 years ago

TI__Mastermind 22610 points

Further details from the Package Thermal group ...

See: http://www.ti.com/lit/pdf/spra953

Theta Ja is rarely sufficient for determining if a device will or will not work in a given system, since Theta Ja is heavily board dependent and the customer owns their board design.

We recommend that the customer use the Psi Jb metric from the device datasheet and their expected board temperature and dissipated power to determine if a given system and device will perform in a thermally acceptable manner.

Tj = (Tboard + (Psi Jb * power))

For LP38500SD-ADJ (WSON / NGS, 8-pins) : Psi(jb) = 26.3°C/W

0 Hirotaka Matsumoto over 9 years ago in reply to Donald Jones

Guru 27525 points

Hi Donald San,

Thank you for your reply!
We will check these contents, and if we have some questions, we will ask you them.

Kind regards,

Hirotaka Matsumoto

Power management

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LP38500 － Board layout for best thermal resistance for exposed package