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LP5907 – About an acceptable capacitance [uF] and ESR [ohm] value of output capacitor

Guru 21045 points
Other Parts Discussed in Thread: LP5907

Hi Team,

 

Our customer are evaluating LP5907 at the following conditions.

 

[condition]

-Vin=5.5V (or 5.0V)

-Vout=4.5V

-Iout=250mA

-Cin=47uF

-Cout=200uF (Ceramic capacitor)

 

They understand that this Cout value is out of a recommended range.

However, they have to use it at the following conditions to decrease the noise of the output.

Therefore, they would like to know the stability of LP5907.

 

Could you please let us know the calculating formula to calculate the phase margin?

Specifically, we would like to know the influence that the capacitance and ESR value of output capacitor gives to the phase margin.

 

If you contact to below my e-mail address or let me know your e-mail address,

I can send the customer information.

I’m looking forward to hearing from you.

 

[my e-mail address]

Kanemaru-h@clv.macnica.co.jp

 

Regards,

Kanemaru

  • Hi Team,

     

    Could you please let us know the current status regarding this question?

    We would be grateful if you could reply as soon as possible.

     

    Regards,

    Kanemaru

  • " ... Could you please let us know the calculating formula to calculate the phase margin? ..."

    There is no formula available for calculating LP5907 phase margin. Ringing of the output voltage due to a load step transistion is used to determine loop stability, and estimate the phase margin.

    http://www.ti.com/lit/an/slva381b/slva381b.pdf

    http://www.ti.com/lit/an/slva115/slva115.pdf

     

  • Hi Donald-san,

     

    Thank you for the information!

    I have one more question.

     

    --------------

    [Question]

    The following content is mentioned in datasheet.

     

     

    How did you decide the recommended capacitor(1uF to 10uF) and ESR(5mohm to 500mohm) value?

    We understood that you have the grounds to decide this value.

     

    For example, we would like to know the following value which is needed for stable operation.

    -P(Load) pole =1/(2*pi*Cout*(Vout/Iout)) is form ??kHz to ??kHz

    -Z(ESR) = 1/(2*pi*R(ESR)*Cout) is from ??kHz to ??kHz

    --------------

     

    So, if this goes on, they can’t design it if there is no information.

    Therefore, We would like to know this information.

    Could you please let us know it?

    I’d greatly appreciate your verification.

     

    Regards,

    Kanemaru

  •  " ... How did you decide the recommended capacitor (1uF to 10uF) and ESR(5mohm to 500mohm) value?..."

    The original design team is no longer here to answer these questions about why they designed it the way they did.

    I would presume that the output capacitance range and ESR range was a part of the original design target, or perhaps a requirement from a lead customer, and was likely validated via simulation.

    The 'Load pole' is an external phenomenon … since we know Vout can be 1.2V to 4.5V, Iout can be 1mA to 250mA, and Cout can be 1uF to 10uF … it’s becomes a spreadsheet exercise to work the range of possibilities.

       10uF, 4.5V, and 1mA gives an Flp of about 4Hz

       1uf, 1.2V and 250mA gives an Flp of about 33kHz

    Plus, there may have been some secondary considerations between max Cout capacitance and how to size the automatic output discharge resistor.

     

     

  • Hi Donald-san,

     

    Thank you always for your kind support!

    I understood. thank you very much.

    We will report the information to our customer.

     

    Regards,

    Kanemaru