Hello;
The datasheet of tps7a8300 says the power good function is not valid when feed forvard capacitor is used.
However in the evaluation module, both feedforward capacitor used and power good function is used.
What does the datasheet mean by "valid"? I need power good signal in right time for power sequencing with system fpga.
Hello,
What we mean in the datasheet is that when using a feed-forward capacitor, CFF, there is the possibility of falling on an invalid state, that is, having the PG signal come to a ON state before the VOUT does due to the time delay caused by CFF. As such is the case in the figure below:
Source: Application Report, "Pros and Cons of Using a Feed-Forward Capacitor with a Low Dropout Regulator" (TI Document: SBVA042)
In Figure 9a PG is asserted after a delay, tref, at that point VOUT is at an acceptable level, however in Figure 9b, PG also goes up after a delay tref, but VOUT is not fully ON, which might result in getting a PG signal before your VOUT is ON (invalid case).
As the datasheet mentions, “To avoid this issue and receive a valid PG output, ensure that the time-constant of both the LDO and the power-good output match.” For more details refer to section 2.1 of the following application report: "Pros and Cons of Using a Feed-Forward Capacitor with a Low Dropout Regulator" (TI Document: SBVA042)
