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TPS7A8300 & TPS7A85 Enable Timing

Other Parts Discussed in Thread: TPS7A85

Regarding the TPS7A83000 and TPS7A85 LDOs, do we have information concerning the min/max or at least typical values for how long the EN rising and falling edges take to enable and disable the device, respectively?

This timing information is needed to determine power sequencing requirements involving these two LDOs.

Thanks, David

---------------------------------
David Hildebrand
Analog Field Applications
South Region
Texas Instruments, Inc.
Office:  214-479-0917
Cell:       972-841-6499
david.hildebrand@ti.com
---------------------------------

  • Hi David,

    The startup time and shutdown time will vary with conditions such as Cnr/ss.  The following figures are provided in the TPS7A83 datasheet to help give an idea of timing.  Please note that the time scale is different between the two curves.

    Very Respectfully,

    Ryan

  • Ryan,

    Thanks.  This is very helpful information.

    This info covers the EN start-up / enable) timing, but not the EN disable timing.  Can you provide similar graphs for the disable timing, shown relative to the EN falling edge?

    David

    ---------------------------------
    David Hildebrand
    Analog Field Applications
    South Region
    Texas Instruments, Inc.
    Office: 214-479-0917
    Cell: 972-841-6499
    david.hildebrand@ti.com
    ---------------------------------

  • Hi David,

    The delay between the the enable signal changing state and the output beginning to respond will be similar to enabling; however, it may not be as clear depending on loading conditions and output capacitance. The capacitors will hold the output up after the LDO disables.

    As both startup and shutdown are application dependent, prototyping is highly encouraged. The EVMs for each product can be modified to match the application capacitance, voltages and load.

    Very Respectfully,
    Ryan