TPS7A49: Latch up condition_Output go to zero instead of 5 VDC

Part Number: TPS7A49

Any Idea?? 

At some point during normal operation, LDO latch up at zero out voltage causing the entire cct. to be OFF

Attached both schematic and screen shoot....

  • Hi,

    Thank you for providing a schematic and a scope shot, this is always very helpful when we are debugging things. Unfortunately I'm a bit confused because I don't see any improper behavior in the scope shot you provided. The output is always at 5V when Vin/Ven are up. One thing I would note is be careful when connecting a scope probe or anything else to the NR/SS pin. This pin cannot support much current being drawn from it and can collapse. Since Vout tracks the NR/SS voltage, any reduction in the NR/SS voltage will cause a proportional decrease in the Vout voltage. This may not be related to the problem you are having but be aware that it can happen. 

    Also, I reviewed the schematic and I don't see a problem there, so if you could provide a scope shot showing the problem hopefully we can trace the problem from there. 

    -Kyle

  • In reply to Kyle Van Renterghem:

    Thanks Kyle for the quick answer!

    Unfortunately I don't have a pics for the failed LDO I/Os because it's installed on products where used in an Oil Fields.
    But one more thing to add, after LDO there is an IC supplied by this LDO and it's max input voltage is 5.5 V and we found that some of them had the mentioned issue above while others blown the other IC (5.5V one). So in this case for some reasons two thing may happened:
    1- LDO Vout goes above 5.5V and blown the next IC which supplied from it.
    2- LDO holds the output at zero volt and causing the cct to be off (and this confirmed by cycling the power to the LDO-marked S+10 in my schematic and will start functioning normally).

    RCA ongoing as we do have more than 20 product having the same issue in the field with different loads attached to them.

    I have some questions please:

    1- Do you think if I will change its In V from 10 to 7 will make any difference (I am trying to decrease the dropout resistance across the pass element, the load of the LDO consumed 1 to 5 mA)?
    2- Do you have an idea, based on generally CFF (C4 in my schematic) selected?
    3- The output load attached to this LDO non-switching, Is it possible and will be a good thing to increase the soft start time by increasing NR/SS cap and how much the max value allowed?

    Thanks Kyle again and have nice morning!
    Marwan
  • In reply to Marwan Al-Dulaimi:

    Hi Marwan,

    I'm working on getting a TPS7A49 setup on a board so I can do some experiments with it to see if I can replicate your issue. In the mean time I had a question and wanted to answer the questions you asked.

    Is it possible that the input voltage is drooping putting the device into dropout without going all the way to 0V? I ask because when an LDO comes out of dropout the FET is fully on and the output will overshoot some before the loop can detect the overshoot and turn the FET off. 

    1- Do you think if I will change its In V from 10 to 7 will make any difference (I am trying to decrease the dropout resistance across the pass element, the load of the LDO consumed 1 to 5 mA)? If the input voltage is drooping and putting the device into dropout, reducing the input voltage to 7V may help reduce the overshoot. Nothing regarding the LDO will be negatively affected by reducing the input voltage so you have 2V of headroom instead of 5V. 

    2- Do you have an idea, based on generally CFF (C4 in my schematic) selected? We usually recommend 10nF-100nF for Cff caps, stronger AC coupling between the output and the feedback node can have unintended negative consequences. If you're interested in learning more about affects of using Cff caps you can read our application note Pros and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator 

    3- The output load attached to this LDO non-switching, Is it possible and will be a good thing to increase the soft start time by increasing NR/SS cap and how much the max value allowed? I'm not sure what you mean by the load attached to the LDO is non-switching. Usually Cnr is used to control the inrush current which charges the LDO's output cap (plus any other decoupling caps on the LDO's load). If the LDO's input voltage is drooping during startup then you may want to use a larger Cnr. We usually recommend between 10nF-1uF for Cnr. With Cnr=1uF the startup time would be 1.4 seconds which is often longer than most applications want to wait. 

  • In reply to Kyle Van Renterghem:

    Hi Kyle,

    Thanks for your prompt answer!

    That's will be great if you could replicate the issue on your breadboard setup and I will provide you with all our circuit work environment as may play the role in there.

    In regards to your question, I would say that I am doing experiments on both a real product and a breadboard  and yesterday we went through this check on the breadboard setup as below:

    We give a 11.15 V to the input of LDO as designed by a real product PWR supply to give then decrease the voltage below Vout and we found that Vout following Vin (below 5 Vin) and that's what I've understood it's a normal behaviour for this chip.

    But between (1 V - 2.5 V) the LDO output start switching with unstable behaviour (below its dropout voltage) as we trying to test the UVLO cct inside the LDO if will gets lock or not, and then as long the voltage will go more than Vdropout (~2.5VDC), LDO will follow its input again. I hope this answered your question but one thing I am not sure if you want to hold the input below its Vdropout and more than zero for how long in order to force the pass element in a switching mode condition? I will try again this test and let you know.

    One pic from yesterday's test showing (Vin , Ven , Vout , and V@NR/SS pins in sequence): as we expected increasing in its SS (Cnr = 1 uF) but I never see any problem if we have a stable load after power up on keep our soft start time ~1.5 mS? 

    More questiones:

    1- Is it possible to add a series cap to Cnr pin instead of one (Just in case a leakage from one cap will force VREF to go to zero and shutdown LDO)?

    2- How much the Vdrop for this LDO (TPS7A4901DGN) ? and how much a good headroom voltage to leave for this chip to make functioning normally?

    Many thanks Kyle for this kind support!

    Marwan

  • In reply to Marwan Al-Dulaimi:

    Marwan,

    See my answers to your questions below: 

    1- Is it possible to add a series cap to Cnr pin instead of one (Just in case a leakage from one cap will force VREF to go to zero and shutdown LDO)? Replacing a single Cnr cap with multiple caps in series shouldn't pose any sort of issue for the device. If you suspect the caps on the board may have a significant amount of leakage you could also add a resistor between NR/SS and the Cnr pin (this would be my preferred method, with the series caps the voltage on the node between the caps is not explicitly defined since there is no DC path to GND or any other voltage/node). 

    2- How much the Vdrop for this LDO (TPS7A4901DGN) ? and how much a good headroom voltage to leave for this chip to make functioning normally? The dropout voltage for this devise is specified to be less than 600mV at the full load of 150mA. You mentioned that the load is 1-5mA, so it might be more helpful to use the typical graph showing Vdo vs Iout which I've included below. From this you can see that the typical dropout would be approximately 100mV at 5mA. As long as Vin>Vout +Vdo the device will function normally, though PSRR does suffer with lower headroom voltages (Vin-Vout). Assuming there aren't any big input voltage transients and you don't need/want to filter much noise from the input supply, I'd estimate that if Vin>5.25V you should be fine (though you would obviously want to verify that with your application specific testing. 

    Regarding the test you performed, it would be best to allow the LDO to startup and reach it's regulated voltage and then perform the test dropping the input so it is a bit below the regulated voltage (~4.5V) and then bring the supply back up quickly. If the edge rates on this are fast enough LDO's will overshoot when they come back out of dropout. I put together a quick timing diagram to help you visualize the test and behavior. 

    Also, I had a thought on the devices with Vout=0V. You mentioned these being in an application in an Oil field, is it possible that dirt of other particles could build up around the device and cause leakage currents to flow between device pins? If this is a possibility, as we discussed before the NR/SS pin is sensitive to external leakage and if there were to be a leakage or low resistance path between NR/SS and DNC or any GND node, then the output of the LDO would likely be 0V. Let me know your thoughts.

    -Kyle

  • In reply to Kyle Van Renterghem:

    Thanks a lot Kyle for your thoughts, it's highly appreciated!

    I will go through your notes and keep you updated ASAP.

    Warm Regards,
    Marwan
  • In reply to Marwan Al-Dulaimi:

    Hi Kyle,

    I hope that you had a great weekend!

    Thanks for your answers in regards to my last reply.

    As you mentioned about using our products in oil fields, Now I also simulating the environment (environmental test), humidity, moisture, temperature trying to replicate the failure in the lab and I will give the results very soon.

    And I attached to you a pic from the scope explaining how does LDO behave while decreasing Vin to about 4.25 V then ramp this voltage up to 11 V, it seems a stable generation in the output signal and follow up the input if it goes below 5.2 V (CH1 Vin, CH2 Vout).

    More questions please:

    1-  What is the behaviour of the LDO if NR/SS pin to GND less than -0.3 and greater than 2 V,Second, How possible this voltage go above 2 V from the internal LDO cct.?

    2- You mentioned NR/SS is very sensitive to any leakage, do you have an idea how much it's sensitive (how much current will allow to go through and then after this value will cause a problem to this chip)? 

    3- There is a similar topic regarding this lock out mode in this forum //e2e.ti.com/support/power_management/linear_regulators/f/321/t/542669?tisearch=e2e-quicksearch&keymatch=disable 

  • In reply to Marwan Al-Dulaimi:

    Marwan,

    1-  What is the behaviour of the LDO if NR/SS pin to GND less than -0.3 and greater than 2 V,Second, How possible this voltage go above 2 V from the internal LDO cct.? It is not possible for the internal NR/SS pin circuitry to cause the voltage on this pin to be greater than 2V under normal operating conditions.  If the NR/SS pin were to be pulled more negative than -0.3 it could turn on internal diodes and the output would probably show 0V. If the current carrying capacity of those internal diodes was exceeded they could be damaged. If the NR/SS pin were to be pulled higher than 2V the internal circuitry could see electrical overstress (EOS) damage caused by exceeding the breakdown voltage of the internal circuitry. It is more difficult to say what the output would do in this case but most likely it would either be pulled to the input voltage or to 0V. 

    2- You mentioned NR/SS is very sensitive to any leakage, do you have an idea how much it's sensitive (how much current will allow to go through and then after this value will cause a problem to this chip)? I'd expect leakage currents in nano-amps to have an effect on the output voltage accuracy, it may take micro-amps for it to be pulled close to 0V.

    Regarding your 3rd bullet that is related to the TPS7A16 family of devices which are substantially different than the TPS7A49 family of devices. 

     

    -Kyle

  • In reply to Kyle Van Renterghem:

    Thanks Kyle!

    I am sorry for the late reply as I am trying to finalize this  RCA.

    Some development was done on this issue so far which may leads to other questions please:

    1-  TPS7A49 LDO enters to lock mode which send no output voltage (0V) IF NR/SS pin leak through/from EN or Vin pins. In our design EN pin routed underneath NR cap which caused a leakage at some point during it's operation then locked this LDO (schematic attached), while TI recommends to route EN pin through VIA to the bottom layer. 

    2-  My question comes here, This IC you know has UVLO, Thermal shutdown, Current Limit. How this pin (NR/SS) gets one of those safety conditions lets say and locked the LDO output voltage if leaked from/through EN or Vin pin? Sorry my question it seems a bit confusing but I would like to re-phrase it and keep it's original above to give more explanation as may this happen to other customers. So, from LDO's internal circuit, Is this situation leaking between NR/SS & EN pins will force it to go to 0 Vout? I just wanna make sure is TI aware of this firstly and, secondly I would to have a details about how this will happen internally (error amp or pass element).

    3-  Some not all of the failed LDOs found that  they have a drift on their output voltage, designed to give 4.96 V while we measured 5.29 V and even increased accordingly in both Vnr/ss, Vfb. Do you think this failure have an effect and causing this LDO to drift? other designs use same layout and components and their tolerance which delivering 4.94 V and that's expected but I am really concern about the ones which having a drift?

    Thank you so much Kyle for your support!

    Marwan

  • In reply to Marwan Al-Dulaimi:

    Hey Marwan,

    1-  TPS7A49 LDO enters to lock mode which send no output voltage (0V) IF NR/SS pin leak through/from EN or Vin pins. In our design EN pin routed underneath NR cap which caused a leakage at some point during it's operation then locked this LDO (schematic attached), while TI recommends to route EN pin through VIA to the bottom layer.

    It's possible for these devices showing 0V on the output that since it's creating a connection to the Vin node, that if the resistive path was low enough this could cause the NR/SS pin to be pulled up higher than it's abs max voltage of 2V which could cause permanent damage to the reference circuit.

    2-  My question comes here, This IC you know has UVLO, Thermal shutdown, Current Limit. How this pin (NR/SS) gets one of those safety conditions lets say and locked the LDO output voltage if leaked from/through EN or Vin pin? Sorry my question it seems a bit confusing but I would like to re-phrase it and keep it's original above to give more explanation as may this happen to other customers. So, from LDO's internal circuit, Is this situation leaking between NR/SS & EN pins will force it to go to 0 Vout? I just wanna make sure is TI aware of this firstly and, secondly I would to have a details about how this will happen internally (error amp or pass element).

    The LDO does not have a protection circuit similar to UVLO or  thermal shutdown that would protect against this sort of problem. As I mentioned to the first question above it seems like the reference is being damaged.

    3-  Some not all of the failed LDOs found that  they have a drift on their output voltage, designed to give 4.96 V while we measured 5.29 V and even increased accordingly in both Vnr/ss, Vfb. Do you think this failure have an effect and causing this LDO to drift? other designs use same layout and components and their tolerance which delivering 4.94 V and that's expected but I am really concern about the ones which having a drift?

    It seems like for this failure modes there is enough of a resistive path between NR/SS and the enable/input pin to pull the reference higher than the normal 1.2V but not so high that it is damaged. If the reference is higher then the output will be higher as well. The amount the output goes up will be a gained up amount compared to the difference between the normal reference voltage and the pulled up reference voltage. 

     

    -Kyle