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LP5912-Q1: About output cap

Part Number: LP5912-Q1
Other Parts Discussed in Thread: LP5912

Hi,

Let me talk about the output capacitor and output voltage of LP5912-Q1.
Could you confirm the attached file.

LP5912-Q1.pdf

When Cout is 1 μF, the output ripple is large.
When Cout is changed to 3.3 uF, this phenomenon disappears.

I would like your advice on this reason.

Best Regards,
Yusuke / Japan Disty

  • Hello Yusuke-san,

    Sounds like the output is oscillating.

    Please describe the 1uF capacitor used for Cout. Manufacturer, case size, and part number.

    If case size is small it may be that the applied dc voltage from LP5912 Vout is causing the effective capacitance to fall below minimum allowed.
  • Daddio-san,

    Thank you for you response.
    I will describe capacitor information below.

    C128/C127 GRM188R71C105KA12D
    psearch.en.murata.com/.../GRM188R71C105KA12#.html

    I think that the DC bias characteristic probably has no problem.
    Is there something that is considered to be the cause of that?

    Best Regards,
    Yusuke / Japan Disty



  • 1.0µF ±10% , 16V, 0603, X7R

    Yusuke-san,

    I agree with your assessment that dc bias is not likely to be the problem.

    Since low Cout is the typical reason for output oscillation, it becomes a challenge to determine what alternate reason may be.

    Other issues, in no particular order, could be:
    > less than ideal PCB layout, especially with respect to GND at device pin 5,
    > via's in series with Cout adding resistance, or inductance, which can behave like high ESR,
    > unusual (or unexpected) load characteristics,
    > marginal/low Cin value,
    > other undescribed

    My apologies for not having a definitive corrective action.

  • Daddio-san,

    Thank you for you kind support.

    I have two questions from customers.
    1.The problem was solved by changing out put cap 1.0uF to 3.3uF.
         Customers want to know the reason.
      Customers doubt the recommended values(0.7~1uF) in the data sheet.

    2. About  recommended ESR 
           ESR depends on frequency.
           Please tell me the frequency band that recommends this value(5~500mΩ).


     
    Best Regards,
    Yusuke / Japan Disty

  • Yusuke-san,

    1) Yes, LP5912 output is stable with 1uF

    The LP5912 EVM uses the Murata GRM188R71A105KA61 (1µF, 10%, 10V, X7R, 0603) for both Cin and Cout.

    The LP5912 EVM with same 1uF capacitor was used  to capture the Typical Characteristics in the LP5912 datasheet (unless otherwise stated).

    Increasing the Cout value lowers the load pole frequency (1 / (2 x pi x Cout x Rload)) which lowers the max operating frequency of the control loop..

    2) ESR @ 100 kHz.

    Technically, there is some slight variation with load current that could push it out to 500kHz, but for practical purposes 100kHz.

  • Daddio-san,

    Thank you for your kind support.
    Customers are using LP5912-Q1 according to datasheet.
    Nevertheless, the device is oscillating.
    5873.LP5912-Q1.pdf
    (The output ESR is about 80 mΩ.)

    Is there something that is considered to be the cause of that?
    Customer wants to know why oscillation stops by installing 3.3~10uF.

    Best Regards,
    Yusuke / Japan Disty

  • Yusuke-san,

    The provided customer schematic is normal.

    There is no obvious reason for any output oscillation based on the information provided.

    Perhaps some unusual layout in the PCB ground path.

    Perhaps there is something unusual in the load that could be causing this oscillation. Inductive type loads could possibly cause oscillations.

    Otherwise, I have no idea why this is happening.

  • Daddio-san,

    Thank you for you response.
    I have PCB layout, however I do not want to open it in public.
    Can you give me e-mail address for further communication.
    (My e-mail address : tsukui-y@clv.macnica.co.jp)

    Best Regards,
    Yusuke / Japan Disty


  • Yusuke-san,

    The entire PCB layout is not needed or desired. Only the area around the LP5912 showing Cin, Cout, and how they interconnect to the device pins.

    I do not think that PCB layout is likely the issue. Historically I have found, perhaps, one error in every one hundred PCB layout reviews done for LDO's.

  • Daddio-san,

    Thank you for your help and support.
    The reason that output voltage looks like oscillation was load transient.
    Let me ask you one more thing.
    Could you please check the attached file?

    LP5912-Q1 Transient response.pdf

    Can it occur with the load transient response spec of LP5912Q?
    Could you check this case on the condition of Slew rate≒ 800mA/us order?
    Customer wants to confirm that this phenomenon is due to load transient issue.

    Best Regards,
    Yusuke / Japan Disty

  • Based on the described load steps and slew rate, yes, this could be expected load transient behavior.

    Two issues: 

    1) Stated slew rate of the load appears to exceed the bandwidth of the LP5912 control loop. The control loop is not able to ramp up, or ramp down, the current fast enough to hold the output voltage constant. When the control loop falls behind, the output capacitor sources or sinks current to hold the output voltage steady for a period of time. This would be why having a larger output capacitor is helpful in this situation.

    2) 'No Load' (i.e. 0mA) is a special case that marks the end point of the control loop operation where the pass element is totally shut off. This introduces a small delay time to get the control loop back into a linear operating range when load current steps from =0ma to >0ma. This is not a problem if load step rise time is more than approx.2us.

    Note that the LP5912-Q1 datasheet load transients are specified with 10us rise/fall times, with 5mA minimum load currents. Faster rise/fall times will produce larger transients in the output voltage.

  • Daddio-san,

    Thank you for your reply.
    Customers also want to confirm this problem with the spice model.
    Is this reproducible by spice model simulation?
    I do not have software to run the spice model.
    Therefore, I want your advice.
    www.tij.co.jp/.../toolssoftware

    Best Regards,
    Yusuke / Japan Disty


  • Yusuke-san,

    Most of the LDO pspice models are behavioral type models, the LP5912 included.

    That means that most functions are ~ideal~ within the operating range defined in the datasheet, and do not match the silicon behavior exactly, if at all.

    I do know that most LDO models do not include gain/phase accurate models of the control loop. So I would not expect load transient behavior to be accurately modeled. Especially with load transients that have rise/fall times faster than the datasheet specifications.