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TPS7B63-Q1: The WD_EN operation of TPS7B63-Q1

takahiko yokota
Mastermind 7135 points
Part Number: TPS7B63-Q1

Hi

Please let me confirm the operation about WD_EN of TPS7B63-Q1.
There are the following descriptions in 7.3.7.5 Watchdog Enable (PG and WD_EN).
If WD_EN was Low before PG is high, does the watchdog  operate correctly?
"an external microcontroller or a digital circuit can apply a high or low logic signal
to the WD_EN pin to disable or enable the watchdog. A low input to this pin turns the watchdog on, and a high input turns the watchdog off."

Best regards,
Yokota
  • 0
    TI__Guru 55940 points

    Hi Yokota,

    When PG is logic low, the watchdog is disabled regardless of /WD_EN.  After PG transitions to logic high, the watchdog will be enabled when /WD_EN is logic high and disabled when /WD_EN is logic low.  If /WD_EN is logic low before PG transitions to logic high and /WD_EN remains logic low, the watchdog will be disabled.

    Very Respectfully,

    Ryan

  • 0 in reply to Ryan Eslinger
    Mastermind 7135 points

    Hi Ryan-san

    Thank you for the reply.
    Please let me ask you additionally.

    Are there the restriction time that WD_EN becomes Low from High after PG became High?

    Is my understanding correct that watchdog is enable even if WD_EN was high in short time during WD Initialization like the attached document?

    TPS7B63-Q1.pdf

    Best regards,
    Yokota

     

  • 0 in reply to takahiko yokota
    TI__Guru 55940 points
    Hi Yokota-san,

    The watchdog will remain disabled until /WD_EN is transitioned to logic low. There is time restrictions on when the watchdog must be enabled after PG goes logic high. You could leave the watchdog disabled (/WD_EN logic high) if you desire.

    You are correct that once the watchdog is enabled, the watchdog should remain enabled even if WD_EN temporarily goes logic high.

    Very Respectfully,
    Ryan
  • 0 in reply to Ryan Eslinger
    Mastermind 7135 points
    Hi Ryan-san

    Thank you for the quick response.
    Could you tell me the specific times below?

    ・The allowed time that WD_EN temporarily goes logic high to stay watchdog enabled
    ・The restriction time to go WD_EN logic low after PG turned high

    Best regards,
    Yokota
  • 0 in reply to takahiko yokota
    TI__Guru 55940 points

    Hi Yokota-san,

    We do not have characterization data on how long a temporary high on WD_EN can be for the watchdog to remain enabled.  If WD_EN is logic high for an extended period, the watchdog will reinitialize after WD_EN returns logic low.

    I apologize, my previous response is missing a critical word.  There is no time restriction on when WD_EN goes logic low after PG goes logic high.

    Very Respectfully,

    Ryan

  • 0 in reply to Ryan Eslinger
    Mastermind 7135 points

    Hi

    Thank you for the reply.
    Let me ask you a question additionally.
    Could I design the circuit that WD_EN gose low logic using this device's PG as attached document?

    TPS7B63-Q1②.pdf

    Best regards,
    Yokota
  • 0 in reply to takahiko yokota
    TI__Guru 55940 points

    Hi Yokota-san,

    As neither the gate of the FET nor the GPIO of the MCU should be drawing significant current, PG should be able to drive both; however, I would suspect that you need to remove the capacitor and resistor that you have beneath the device in your drawing.  We have not attempted such a circuit so we highly recommend that you prototype the circuit; however, we would expect it to work as long as you remove the cap and resistor.

    Very Respectfully,

    Ryan