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Hi Yokota,
When PG is logic low, the watchdog is disabled regardless of /WD_EN. After PG transitions to logic high, the watchdog will be enabled when /WD_EN is logic high and disabled when /WD_EN is logic low. If /WD_EN is logic low before PG transitions to logic high and /WD_EN remains logic low, the watchdog will be disabled.
Very Respectfully,
Ryan
Hi Ryan-san
Are there the restriction time that WD_EN becomes Low from High after PG became High?
Hi Yokota-san,
We do not have characterization data on how long a temporary high on WD_EN can be for the watchdog to remain enabled. If WD_EN is logic high for an extended period, the watchdog will reinitialize after WD_EN returns logic low.
I apologize, my previous response is missing a critical word. There is no time restriction on when WD_EN goes logic low after PG goes logic high.
Very Respectfully,
Ryan
Hi
Hi Yokota-san,
As neither the gate of the FET nor the GPIO of the MCU should be drawing significant current, PG should be able to drive both; however, I would suspect that you need to remove the capacitor and resistor that you have beneath the device in your drawing. We have not attempted such a circuit so we highly recommend that you prototype the circuit; however, we would expect it to work as long as you remove the cap and resistor.
Very Respectfully,
Ryan