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TLV733P: for layout review

Part Number: TLV733P

Hi team,

Can you review if below layout of TLV73318P is okay?

-. VIN = 3.3V, CIN = 1uF, EN is tied to VIN

-. VOUT = 1.8V, COUT = 4.7uF

Thanks,

Sam Lee

  • Hi Sam,

    It is a bit difficult to see in this format, but it looks like your input and output capacitors are on the opposite side of the board than the LDO.  While TLV733P is stable without any external capacitors and may therefore be okay with the capacitors on the opposite side of the board for this application, the best practice for any LDO is to place the capacitors on the same side of the board as the LDO as close to the LDO pins as possible.  It is further important to have a direct same layer connection from the ground side of the capacitors to the GND pin of the LDO.  The reason for this best practice is to reduce any ESR and ESL added to the loop due to the resistance and inductance in the trace and vias.

    Figure 40 from the datasheet shows a visual depiction of what we would consider a best practice layout for this LDO.

    Very Respectfully,

    Ryan

  • Hi Ryan,

    Thank you for your review.

    Best Regards,
    Sam Lee