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UA78M: Thermal Power Dissipation

J.Schweiger
Expert 1745 points
Part Number: UA78M
Other Parts Discussed in Thread: LM341

Hello,

I am interested in using your UA78M05 in my application.  I see the datasheet provides thermal coefficients, but does not reference a solder pad size.  Can you help provide additional detail so I can understand how the PCB copper pour affects thermal dissipation?

Kind Regards,

-Jon

  • 0
    TI__Guru 55940 points

    Hi Jon,

    For consistency, all of our linear regulators are modeled on a JEDEC High-K board.  More information about our modeling process can be found in the following application report which is linked to from the footnote under the Thermal Information table.   

    While a JEDEC board gives a consistent board layout for means of comparing two regulators, it is important to note that better thermal performance can be achieved based on your application layout.  As with most linear regulators, the primary heatsink for UA78M is the GND plane to which the regulator is connected.  By maximizing the GND copper attached to the COMMON pin and tab, you will achieve the best thermal performance possible in your application.

    Very Respectfully,

    Ryan

  • 0 in reply to Ryan Eslinger
    Expert 1745 points

    Thank you for the quick response Ryan.  I did read through that SPRA953 document before sending in this question, and have re-read it again.  But it doesn't answer my question as to what size ground plane was used to provide the thermal coefficients.  It does talk about different 'test board types', but I see no mention of ground plane sizing used when making the measurement.  Perhaps I'm still missing the pertinent section of the document, please clarify.

  • 0 in reply to J.Schweiger
    Guru 140200 points
    www.ti.com/lit/ds/symlink/lm341.pdf

    www.ti.com/lit/an/snva036b/snva036b.pdf
  • 0 in reply to kai klaas69
    TI__Guru 55940 points
    Hi Jon,

    The key point to keep in mind is that you should maximize the GND plane size for UA78M in your application in order to pull as much heat from the regulator as possible. It will be your specific application layout requirements that will limit the size of the GND plane so it is difficult to give any other guidance than to connect as much copper as possible to GND.

    Here is our interpretation of the JEDEC High-K board that we use for our thermal metrics. The JEDEC High-K board is a four layer board. The top layer only has traces running straight to the pins of the device. The internal layers are ~5500 mm^2 of 1oz copper internal (one is tied to GND, one is a power plane). The bottom layer (opposite to the IC being modeled/tested) is a thermal relief layer with ~1100 mm^2 of 2 oz copper. The internal GND plane and bottom layer are connected to the thermal tab using thermal vias. The JEDEC standards can be found in more detail at their website www.jedec.org. The specific standard that we use for our thermal modeling is JESD51.

    Very Respectfully,
    Ryan
  • 0 in reply to kai klaas69
    Expert 1745 points
    Thank you for this. Figure 3 in AN-1028 (snva036b) is what I was looking for (chart of thermal resistance JA based on copper pour area). Only downside is it only shows SOT-223 and not the DPAK (not sure if this is being shown in LM341 datasheet; they reference package 'PFM' which isn't clarified). I know this graph is included in many LDO datasheets (including your linked lm341), which is why I'm concerned to use a thermal resistance without copper pour referenced in UA78M datasheet.

    Is it safe to use information for a package type across different products? Without documentation in the UA78M I'm hesitant to assume this SOT-223 is the same as the SOT-223 tested in AN-1028. (and I'm leaning towards the DPAK for better dissipation anyway)
  • 0 in reply to J.Schweiger
    TI__Guru 55940 points
    Hi Jon,

    Unfortunately package type is only one of many factors that influence the thermal performance of a device. Other factors include die size, die location and orientation in the package, mold compound, and more. As such it is not possible to do a direct comparison between two different devices without performing a standardized test on a standardized board. This is why our Thermal Information table in our datasheets are based off of JESD51 as it standardizes the thermal metrics. The general trend of more copper will be consistent (more copper allows for more power dissipation); however, the curves can shift based on device specific factors.

    These types of curves are no longer commonly provided in datasheets as there are also many application specific factors that influence thermal performance such as board layout, ambient temperature, air flow, proximity to other power dissipative devices, etc. The current trend is to provide metrics based on a standardized board and testing method such as JESD51.

    Very Respectfully,
    Ryan