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switch power PSRR calculation and TPS56121 external clock settings
how to calculate switch power PSRR?
I am working on TPS56121 now,
from the spec, the open loop gain is more than 60. is there any way to estimate this design PSRR?
TPS56121 have no external clock synchronies, if a design need 4 TPS56121, how can I balance input current in different time?
Is the PSRR of the error amplifier what you are concerned? The error amplifier is powered by an internal linear regulator, not directly from VIN. But the voltage ripple on VIN of each TPS56121 is not preferred because it may cause nuisance overcurrent protection of the high-side FET, especially when you have 4 TPS56121. Therefore, each TPS56121 should have sufficient input capacitors and placed closely to VIN and GND of the IC. If necessary, you may also consider to add input filters.
sorry I concerned about switch power PSRR, like LDO PSRR.
I don't know if switch power have PSRR parameter, if have, how to calculate it?
if there are 4 TPS56121, and place nearby, when they open the high-side FET at same time, there will be a high current on Vin.
so is there any way to assign these 4 high-side FET opening at different phase and at same frequency?
Switch mode power converters don't have PSRR. To evaluate how the change in input voltage affects output voltage, the line regulation for DC, line transient response for high frequency, and line-to-output transfer function (i.e. audio susceptibility) are used. Since this performance heavily depends on the system design, e.g. feedback loop, input/output capacitors, PCB layout and etc, these parameters are not given in the IC's datasheet, but possibly measured on the evaluation modules. For TPS56121, the line regulation performance is shown in the EVM user's guide.
As you mentioned before, the TPS56121 does not support synchronization. To minimize the interference between each TPS56121, the input capacitors play important part to handle the switch current. The RMS current in the input capacitors = Iout x sqrt (D*(1-D)), where D = Vout/Vin.
For each TPS56121, the input voltage ripple can be calculated as the sum of the ripple due to input capacitance and that due to the equivalent series resistance (ESR) of the capacitors.
Ripple due to input capacitance = Iout *Vout/(Vin * Fsw * Cin)
Ripple due to ESR = (Iout + (Vin-Vout) * Vout/(2* Vin * Fsw * L)) * ESR
Thanks for your help.
If the output current is too high, we use external clock with different phase to synchronize and reduce the input ripple.
Can I use EN pin to let 4 TPS56121 top MOSFET work at different phase?
Or I add some more input Capacitor near the ICs?
which way is better?
I don't think you can use EN pin to control 4 TPS56121 work at different phases. For synchronization or phase interleaving, we would need to get access to initiate every PWM pulse, TPS56121 does not have the feature. By pulling EN down, the TPS56121 will be disabled; leaving EN floating, the TPS56121 will start up with a timing described in Figure 19 of the datasheet.
I think adding more input capacitors near the ICs would be an option.
thank you very much for answers.
waiting for the external clock at TPS56121
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