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Ground connections for TPS63001
Dear TI team and others,
I would like to verify that my board layout using TPS63001 (3.3 V fixed-output buck-boost regulator used with a single-cell Li-ion battery source) is correct.
For this purpose, I am attaching two images below: The 1st image shows the actual main board layout of the regulator (using EagleCAD). Both the relevant pins and attached parts are labeled, and the ground trace is color-highlighted as well as labeled "--G--". (In addition, for reference, I attached the 2nd image showing the corresponding circuit schematic.)
Specifically, I have two questions:
(1) Is everything as it should be in terms of the ground connections GND, PGND, Powerpad, etc.? As you can see in the layout image below, I routed PGND to GND with four vias (thermal) placed along this routed trace; in addition, this routed trace is also shorted to the Powerpad. I am slightly confused by the notes given in the datasheet regarding the connections for PGND versus GND, and the relation in turn to the Powerpad, so any tips here would be appreciated.
(2) Do you recommend any further changes in general for the overall design before I submit this layout for production?
Thank you very much.
Thank you for providing the images in your post. Unfortunately, I do not recommend using this PCB layout design for production.
In regards to your questions:
Is everything as it should be in terms of the ground connections GND, PGND, Powerpad, etc.?
It is recommended that both grounds (PGND and GND) be connected on the PCB at only one point, ideally close to the GND pin. The Powerpad should be connected to PGND.
Do you recommend any further changes in general for the overall design before I submit this layout for production?
Here are some of my immediate concerns looking at your design:
1) Trace width – you want your power traces to be as large as possible. This also applies to the inductor traces/pads. The long skinny traces in your current design are going to reduce the regulators responsiveness to line/load transients as well as the overall stability.
2) Feedback loop – your feedback loop should be kept as short as possible. Also, make sure to keep it isolated from noisy components.
3) Input/output capacitors – your input and output capacitors should be kept as close to the IC as possible. Also, as a general rule of thumb, the output capacitor should be at minimum 5X the value of the inductor.Your current design is not meeting this requirement. I recommend using 20-30uF output capacitance depending on your load transients.
4) To prevent noise from coupling with your ground reference, avoid running ground traces underneath the switch node (which could be L1 or L2 since this is a buck-boost regulator).
5) If you choose to add the 0.1uF C15 capacitor, then I suggest removing the connection between VIN and VINA. This will allow C15 and the internal resistor between VIN and VINA to filter input noise.
I strongly advise you to examine the layout provided in the TPS63001 EVM user guide and model it as closely as your application allows.
Please let me know if you have any additional questions.
Dear Nick, I have incorporated most of the pointers you provided; much appreciated. One doubt remains, so I'm writing to see if you can provide some thoughts on this:
Shorting PGND (pin 3) to GND at only one point and close to the GND pin (pin 9), and yet prevent running a ground trace under the L1 (pin 4) or L2 (pin 2) traces, seems possible only if this were done by simply running a tiny trace directly between the GND pin and the Powerpad (which is of course already immediately connected to PGND). Does this work? (In other words, for this particular aspect, the same as I already have in my prior layout pictured above.)
No problem, I'm glad I could help. I'm tempted to say your GND-PGND connection works, but I will double check tomorrow and let you know.
Thanks in advance for looking into that Nick.
I am particularly curious now because if it were true that one could lay out that most obvious chice for the PGND -> Powerpad -> GND direct connection (in which case, the two corresponding traces for it would be tiny ones both lying within the bounds of the chip profile), then why would the TPS63001 designers have left the option open in the first place instead of designing the chip with the PGND -> Powerpad -> GND connection already pre-shorted in that above manner?
I'm running through the datasheet for the evaluation module another time to see how they accomplished the two ground connections, but it is hard to tell from the layout images on page 6 and 7 of the pdf (see below). The TPS63000-EVM datasheet: http://www.ti.com/lit/ug/slvu156/slvu156.pdf
The GND-PGND connections are surprisingly difficult to describe in words, but based on your comment above (..two corresponding traces for it would be tiny ones both lying within the bounds of the chip profile), I think you have it nailed.
I have attached the original PCB layout pdf (below). I agree, the images copied into the EVM user guide look blurry and are difficult to interpret. Please see the attached PDF for reference, paying special attention to the PGND and GND pin connections and verify that we're on the same page.
Regarding your question:
Why would the TPS63001 designers have left the option open in the first place instead of designing the chip with the PGND -> Powerpad -> GND connection already pre-shorted in that above manner?
The Powerpad's primary function is to provide a thermal outlet for the IC. It's size, location, and conductivity, happen to make it a convenient and effective ground plane available for customers. The majority of the time, you are correct, and the Powerpad will be used as a ground reference, but some applications have unique ground requirements; leaving the connection open allows for more flexibility in end applications.
Dear Nick and others,
There's some good news and bad news.
We have completed the suggestions you recommended, and sent off our PCB for an initial sample production, so will be testing that soon.
However, in the meantime, I had a problem with the TPS63000 evaluation baord. Here's what I did:
I had a few evaluation PCBs produced based on the TPS63000EVM gerber files provided on the website. After I had the parts soldered (TPS63001, so the circuit is simplified), I connected a Li-ion battery to VIN. Within seconds of beginning this test, I noticed that the inductor began to heat up to a extremely high temperature (I'm using 2.2uH, LPS3015 model, as recommended). I also took a quick read on the Vout, and it was fluctuating fairly quickly across values between 0V and 3.4V.
This happened across two boards, so I think the source of the problem might be consistent.
Can you share some thoughts on possible reasons for this?
What did you use for R1 and R2?
Daniel, I shorted R1 (=0 ohms) and R2 left open, as necessary for TPS63001.
What else do you see as a possible culprit for the inductor heating up?
Can you post analog oscilloscope shots of VIn, VOUT, L1, L2, Vout and Vfb for both a working and non working board?
Did you use the BOM from the EVM User's Guide when populating the board? Are your capacitors rated for the correct voltage? Is there a short from the output or one of the pins to ground? What is your load?
Hi, This is a great form on this subject. I was wondering if one of the TI engineers wouldn't mind commenting on my layout and schematic for this chip. We have had a requirement change and are on a tight deadline and we barely have enough time to order this last revision of the baord, we really cannot afford any mistakes. I have uploaded my schematic for the power supply as well as the board layout.
This is the fixed output 3.3V version of the chip. Max supply current 250mA, the 4.7uH Inductor is used because it is the same part used in another power supply on the board. I am really only concerned with the schematic correctness and layout of the TPS63001 on my design, specifically the star point of GND and PGND. GND is the ground for the rest of the board (uProcessor, bluetooth, etc...) There is a ground plane that runs under the whole board, but is not shown in this picture, connection to this plane is with the via to the left of C6 and C5. There is also a VCC plane, not shown, connection to this plane is the via below pin 1 on the TPS63001.
I have attached pictures of both my schematics and layout.
Thank you very much!!
These types of design reviews are best directed to your local FAE.
Your layout actually looks very good. Well done.
You will want to add more output capacitance, per equation 7 in the datasheet. Don't forget to account for DC bias.
I highly recommend testing an EVM with your schematic to avoid any mistakes.
Hi, thanks for the the comments. I will certainly add more output capacitance.
Can you comment further on what the conscerns are with DC bias?
Also, what do you mean by EVM? And how would I go about contacting a local rep for future concerns?
Thanks or being so helpful!
DC bias is a well known concern with ceramic caps. There is much information on it on the web. Basically, the actual capacitance of a ceramic decreases with the applied voltage on it.
EVMs are evaluation modules. We have them for most all of our devices for customers to easily test them. Here is the one for the TPS63000: http://www.ti.com/tool/tps63000evm-148
You distributor would likely have an FAE that can help you.
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