I have one question about RT/CLK pin of TPS54240.
Our customer wants to use both 400KHz and 700KHz switching frequency to avoid RF interference from DCDC switching noise.
So adding the below circuit at RT/CLK pin. (Reference resister value will be changed by FET ON/OFF condition.)
But This circuit has some problem. At FET turn-on condition, It makes DCDC output voltage unstable such as jitter. As a result of verification, the voltage of RT/CLK pin is unstable. So we add the CAP to make it stable as the below circuit.
My question is whether this circuit can occur some problem or not. If this circuit has any problem, please let me know it.
Also if you have other solutions to solve our issue, please advise me what I should do.
Thanks and regards.
The RT/CLK connection is sensitive. We recommend tightly coupling the RT resistor to RT/CLK and GND close to the device. So I am not surprised that you are having difficulties. We have not tried any type scheme that you propose, so i do not know if there are any additional issues. What is the value of the capacitor?
Consumer DC/DC Applications
The value of CAP is 102~103(1nF~10nF).
If any idea, please let me know it.
We are going to run a simulation to see if there are any issues.
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