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Hi there,

When placing an input capacitor to a switcher, should I place it as close to the switcher or as close to the power input connector?  Do I want to get rid of the noise as soon as possible?  or try to minimize the input current loop?

Any help is appreciated!

Thanks,

TC

http://www.ti.com/lit/ds/slusaf8a/slusaf8a.pdf

Power Stage
A synchronous BUCK power stage has two primary current loops. The input current loop carries high AC
discontinuous current while the output current loop carries high DC continuous current. The input current loop
includes the input capacitors, the main switching MOSFET, the inductor, the output capacitors and the ground
path back to the input capacitors. To maintain the loop as small as possible, it is generally good practice to place
some ceramic capacitance directly between the drain of the main switching MOSFET and the source of the
synchronous rectifier (SR) through a power ground plane directly under the MOSFETs. The output current loop
includes the SR MOSFET, the inductor, the output capacitors, and the ground return between the output
capacitors and the source of the SR MOSFET. As with the input current loop, the ground return between the
output capacitor ground and the source of the SR MOSFET should be routed under the inductor and SR
MOSFET to minimize the power loop area. The SW node area should be as small as possible to reduce the
parasitic capacitance and minimize the radiated emissions. The gate drive loop impedance
(HDRV-gate-source-SW and LDRV-gate-source- GND) should be kept to as low as possible. The HDRV and
LDRV connections should widen to 20 mils as soon as possible out from the device pin.