Dear Forum
I am looking to use the TPS54620 on a design where I will power multiple (9) FPGAs (requiring 3.3V, 2.5V and 1.2V) where after power up I am hoping to sync all three converters out of phase using one of the FPGAs to reduce input ripple.
The datasheets shows nicely how to do this with something which looks like a relay but obviously is not practical in real designs
I was hoping I could use a LVC logic buffer which are guaranteed high impedance on the output until powered and output enabled. These buffers can then be enabled by one of the FPGAs after the sync clocks are available. However these high impedance outputs still have a leakage current of a few uA which not knowing the internal structure of the RT circuit I am unsure of the effect this leakage will have on the generated RT frequency especially as the set resistors are such high values (100K+).
1... Has anyone achieved this using a LVC buffer or anything similar (Bus switch)?
2... Why does the data sheet not have a more real life circuit example rather than an idea circuit equivalent?
I thank any help given in advance...
Many Regards
Tony
Hi Tony,
A buffer as you suggest is what we typically recommend to interface the RT/CLK pin with. I tested this with a SN74LVC1G126. I did see an effect of the leakage current when OE is low and there is a clock signal input to A. What happened was the switching frequency shifted by ~10kHz compared to the nominal value when the clock signal at A is turned off. This is because the DC voltage at RT/CLK is slightly shifted from the leakage.
One suggestion we've had previously to reduce the effects of the leakage, but haven't tested, is to use the dual gate version SN74LVC2G126, the first gate with a 10k pull down followed by a second connected to the RT/CLK pin with the RT resistor.
Let me know if you have any additional questions.
Regards,Anthony
DC/DC Power Applications Engineer