Why the Synchronous Buck inductor dipped below sea-level (0A)?

Dear sir,

Hi, there is a TPS5432 be used in my project.

The input voltage is 5V, transfers to output 3.3V/ 1A (peak-peak).

At the heavy load, the minimum inductor current was about 189mA.

But at the light load, I measured the inductor current dipped below "sea-level" (0A) (refer to below picture).

I'm not sure whether it's correct or not. 

Could you help to reply me asap? Thank you :)

  • TPS5432 is a synchronous converter.  Since the low side switching element is a FET, it can pass current in both directions.  This is the signature operation of the synchronous converter.  Non-synchronous converter uses a catch diode that can only source current.

  • In reply to JohnTucker:

    Hi John,

    Could I  know the rated VDS on high side MOSFET? (the datasheet only shows the maximum 7V on PH pin)

    If the VDS spike on high side FET is 7.8V (40ns), will it broke TPS5432 or PCBA?

    Please support to reply me asap, thanks!!!

  • In reply to Hedy Hung:

    The FET is probably a 7V structure.  It does have a transient rating of 10 V for 10 nsec.  That rating is somewhat arbitrary.  7.8 V for 40 nsec is probably ok even though we cannot guarantee it.  I am on holiday until after the new year.  I cannot get you a definitive answer until that time, but I I have seen these requests before.  The official spec is 10 V peak for 10 nsec.  Also, you need to be careful when measuring that. You will need to use the "tip and ring" method to minimize the ground  loop.  can you post your waveform? I monitor the forums even when I am OOO.

  • In reply to JohnTucker:

    Dear John,

    Sorry for interrupting your holiday.

    May I know the 10V for 10nsec is power dissipation rated ability or how it be calculated? The spike waveform of 7.8V for 40nsec please refer to below, and "Math" is VIN minus PH, channel 4 is inductor current.

    Thanks your advice to minimize the ground loop for measuring :) 

    5430.TEK00006.TIF

  • In reply to Hedy Hung:

    The 10 V for 10 nsec spec was probably not calculated.  The process specification only gives dc voltage rating.  that is not practical for dc/dc converter circuits.  there will always be some over/undershoot on the rising and falling edges.  The spec chosen is somewhat arbitrary and represents what we would consider safe an reasonable based on our engineering evaluation tests.  There will always be some application with a little more amplitude or a little longer duration that is probably safe as well.  That being said, your waveform seems a little high.  I cannot tell much about the time, you should probably look at both the rising and falling edge at 10 nsec / div time scale.  if the amplitude does prove too big, you can use an RC snubber to suppress it.

  • In reply to JohnTucker:

    I had measured VDS with 10 nesc/ div as 4370.3.3V_VDS_2.TIF And the result is 7.67V/ 3.4nsec (from sea-level to peak), could you help me to check it's correct or not?

    Btw, I tried RC snubber from the reference design , but I cannot calculate snubber parameters since the CFET is unknown. Is there any way to design? Besides, I had tuned CSnubber to make fSnubber = (1/2) foriginal ringing, but it seems ineffective, I'm so confused about that, please help!! thanks.