Is there a solid technical reason why the TPS54332 datasheet, switcherpro and apparently other recent texas CCM controllers use an unusual variant of type II network? There is no feedback between the error amplifier compensation node and the voltage feedback node. Instead an RC network is connected to ground essentially shorting the EA output at higher frequencies. Therefore you're pretty much at the mercy of the output filter pole & output voltage & load to roll off the feedback gain with no real control over it in compensation stage.
Venable's classic type II would connect the end of the RC net to Vsense pin instead of GND.
This way I could set the "pole at origin" and the DC gain so I can actually control how much gain we have and have a finer control over the crossover frequency without changing inductor size etc.
Is this going to cause problems, however? Assuming I know what I'm doing with regards to designing type II compensation net for UC3842 controllers.. I do realize the TPS54332 uses fsw of 1MHz which is a lot more than UC3842 allows for and might cause some unforeseen highfrequency problems.
The TPS54332 is a current mode control device. The error amplifier is not a regular op amp put instead is a transconductance amplifier. The intended method for frequency compensation is to place the components from COMP to GND. The output voltage of the transconductance amplifier does not directly set the duty cycle, but rather is used to set the value of the pulse by pulse peak current for each individual cycle. That combined with the ramp waveform of the inductor current (and any slope compensation that may be applied) sets the individual duty factor for each cycle.
So far as I know most if not all modern current mode devices made by TI and other manufacturers use the similar topologies with transconductance amplifiers and compensation components placed from the output of the transconductance amplifier and ground.
The type II or type III compensation schemes you reference or more commonly associated with voltage mode control using a traditional error amplifier to set the level into the PWM ramp comparator and thereby set the duty cycle. The UC3842 is an older bipolar process and uses a common error amplifier rather than a transconductance amplifier so type II compensation is appropriate for that device.
Consumer DC/DC Applications
I see. I should research this transconductance style error amplifier a bit more. Almost all available reference documentation is written for usual opamp style error amplifier, thought.
So to come back to my original issue, how would I manipulate the initial amplification rolloff of the transconductance amp in TPS54332? With Type II network with a regular error amplifier it's straightforward enough.
However without a feedback loop in the transconductance amplifier I do not see an obvious way to limit the DC amplification.
I'll answer myself. While the switcherpro doesn't show the low-frequency pole, it is very much there and can be used to control the amplification of the EA.
The datasheet is a bit thin on details, thought. It does not even spell out how to calculate the output filter Fp and Fz.
Also there is no real explanation to the equation 8. I do take it the issue here is actually increasing Q of the double pole at 1/2 fsw (Ridley's more accurate current-mode control paper and Sheehan's current-mode modeling). There is also no mention of how much the compensating slope is so there is no real way to determine minimum acceptable inductor value before you get into trouble.
However switcherpro does indeed show that. I made a 4.3V -> 3.3v smps with 0.5A load and 4.7uH ind, 22uF ceramic cap. With (apparently) inadequate slope compensation the peak at fsw/2 becomes huge. However with 10uH inductor the peak practically disappears which seems a bit unlikely relationship to the double pole. I played a bit with the what if scenarios and there peak seems to go from very large at 6uH to neglible at 9uH.
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