Hello,
Question 1: How can I calculate the modulator gain for TPS40054?
Here are the specifications:
Vin_min=18V, Vin_max=30V, Vout=12V, Iout=6A
I have found the following equations by TI: (http://focus.ti.com/lit/an/slva301/slva301.pdf)
Amod = Vcc / Vramp
Where the Vramp = 2 x (Vcc - 3.48) / (Vuvlo – 3.48)
1) Which value can I use for Vcc? Vin_min or Vin_max
2) Which value can I use for Vuvlo?
Question 2: Value of Resistor Divider
Which value can I use for R1? Data sheet of TPS40054 page 17: tell me 50K to 100K but SwitcherPro use 10K?
Thank you.
Vcc is the input voltage to the voltage feed forward circuit. This is the source voltage to the resistor connected to the KFF pin. In the conventional configuration, this is the input voltage.
Vuvlo is the actual UVLO voltage of the TPS40054 converter as programmed by the resistor feeding the KFF pin. If you are using Switcher Pro, this will be approximately 80% of the minimum input voltage. If you are using the datasheet equations, it is the voltage used in the Rkff equation.
When connected in the conventional mannor (Rkff from KFF to VIN) the modulator gain can be approximated as Amod = Vuvlo / 2
Question 2: Value of Resistor Divider Which value can I use for R1? Data sheet of TPS40054 page 17: tell me 50K to 100K but SwitcherPro use 10K?
The selection of R1 for the feedback is a balance between feedback current (and power dissipation) and accuracy/noise suceptibility. SwitcherPro uses 10k to improve accuracy and reduce noise succeptibility. Customers have sucessfully used resistor values less than 1k in this location.
I would not recommend selecting a resistor above 100k as the input bias current of the error amplifier (Ibias is 200nA max) applies an offset to the ouptut voltage. At 100kOhms, this offset is 20mV (2mV when 10k is selected). Any value between 10k and 100k will provide good performance with lower values generally being selected to provide a minimum load current or high noise immunity.
Peter James Miller
IC Design
Power Management - DC/DC Solutions - Industrial & Communications DC Solutions
Member Group Technical Staff 2008
Many Thanks for your reply. Sorry, but I have some other questions too:
1) How can I understand the crossover frequency? And how can I calculate it? SwicherPro tell me 17,8KHz.
2) I have calculated the f_LC and the f_ESR. (Equation 20 and 21). Now I will calculate the components of type III network: (C3, R3, C2, R2 and C1: with Equation 24 and 25)
But which values can I use for the poles and zeros fp1, fp2, fz1 and fz2?
Thank you. Bizhan Behrouz
Bizhan Behrouz
Don't be sorry about the questions, asking questions is one of the ways we learn.
Cross-over frequency is the frequency where the magnitide of the full loop response (Error Amplifier, Modulator and Power Stage) achieves zero loop gain, it is not easy to calculate in a general sense as it involves the product of two complex variables (Error Amplifier Transfer function and Power Stage Transfer function) In a "well designed" loop, it is the frequency where the L-C low-pass filter's gain is the inverse (or negative if expressed as dB) of the error amplifier's Mid-band gain (typically defined as Rcomp / Rfb2 where Rcomp is the resistor in the series RC network from FB to COMP and Rfb2 is the resistor in the RC network from Vout to FB) times (plus if using dB) the modulator gain we discussed above.
2) I have calculated the f_LC and the f_ESR. (Equation 20 and 21). Now I will calculate the components of type III network: (C3, R3, C2, R2 and C1: with Equation 24 and 25) But which values can I use for the poles and zeros fp1, fp2, fz1 and fz2?
There are probably more methods for selecting these frequencies than power supply designers, each having a few of their own ways of selecting them. One method that can be used is:
The two zeros are selected to bracket the L-C double pole, which is 1/[2*pi*Sqrt(L*C)]. A conservative approach places the first zero at 1/2 this frequency and the second at this frequency. This provides strong phase boost before the L-C double pole and is very effective with ultra-low ESR ceramic ouptut capacitors. For eletrolytic based output converters, both zeros are placed at the L-C pole.
The first pole is then placed at the lower of the the output capacitor's ESR zero at 1/(2*pi*RC) or 1/2 the targeted cross-over frequency, which should be less than 1/5 the switching frequency (1/10 if you're being conservative).
The second pole is then placed at the lessor of 3x the cross-over frequency or 1/2 the switching frequency.
http://focus.ti.com/docs/prod/folders/print/tps40055.html#toolssoftware has a link to the TPS40k Loop Stability tool, which estimates the transfer function (both gain and phase) of the power stage and modulator, compensated error amplifier and full loop and recommends compensation values. While the TPS40054 is not listed, the TPS40055 controller uses the same ramp generator circuit and error amplifier and thus would provide a good bases for a TPS40054 design.
Please note: this tool does not consider the discontinuous operation case and the TPS40054 controller will enter into discontinuous conduction mode at light load as the low-side FET is turned OFF when zero inductor current is detected, so the power stage response will change at load currents less than 1/2 the peak to peak inductor ripple current.
Thank you for your reply. Next question is about input caps:
I have found the following equation for calculate the input capacitor:
C= (I * Vo) / (deltaV * Vin * fs),
Where I= max. output current, Vo= output voltage, deltaV= ripple voltage, Vin= min. input voltage and fs= switching frequency.
(http://focus.ti.com/lit/ug/sluu190/sluu190.pdf page: 8)
Can I use this equation?
I have used 2 x 220µF, 50V (Panasonic EEEFK1H221P, http://www.panasonic.com/industrial/components/pdf/pic_fk_series.pdf )
But both capacitors are going warm. Do you have an idea, what can I do? May the problem be at the RMS current? At the same page you can calculate the max. of RMS current with following equation:
I= Iout * Sqrt (Vout / Vin_min) In my design: I = 6 A * Sqrt ( 12V / 18V)= 4.9A
Best regards
Yes, you can use this equation.
This equation makes 2 assumptions:
1) No AC current is available from the source (infinite AC impedance)
2) Does not account for drop across the ESR of the input capacitor (ESR drop across capacitor is ESR * Iout)
I have used 2 x 220µF, 50V (Panasonic EEEFK1H221P, http://www.panasonic.com/industrial/components/pdf/pic_fk_series.pdf ) But both capacitors are going warm. Do you have an idea, what can I do? May the problem be at the RMS current? At the same page you can calculate the max. of RMS current with following equation: I= Iout * Sqrt (Vout / Vin_min) In my design: I = 6 A * Sqrt ( 12V / 18V)= 4.9A Yes, I believe RMS current is part of your issue. The EEEFK1H221P is only rated for 670mA of current with a 180mOhm ESR. Two in parallels can not support 4.9A. I would recommend you use the first equation with a deltaV of 1/2 * Irate * ESR = 1/2 670mA * 180mOhms or 60mV to size low ESR ceramic capacitors to place at the power stage (Drain of high-side FET to Source of low-side FET) This will limit the RMS current in the bulk capacitors to less than 1/2 their rated ripple current.
Yes, I believe RMS current is part of your issue. The EEEFK1H221P is only rated for 670mA of current with a 180mOhm ESR. Two in parallels can not support 4.9A. I would recommend you use the first equation with a deltaV of 1/2 * Irate * ESR = 1/2 670mA * 180mOhms or 60mV to size low ESR ceramic capacitors to place at the power stage (Drain of high-side FET to Source of low-side FET) This will limit the RMS current in the bulk capacitors to less than 1/2 their rated ripple current.
Ok, but I have already used 2 x 4.7µF, 5mOhm, 50V ceramic capacitors at the power stage (murata, GRM32ER71H475KA88L, Datasheet: http://www.murata.com/catalog/c03e2.pdf) and they are connected from Drain of high-side FET to GND (also to Source of low-side FET) like suggestion in SwicherPro circuit too.
If you agree and it is really no problem for you, I can send you my schematic separately and other information, which you need.
best regards, Behrouz
I welcome your schematic if you wish to send it to me privately, but it's not necessary at this point.
When you use the C calculation above based on the ripple voltage I estimated, what capacitance do you calculate?
I actually realized I dropped the ripple waveform component to the RMS current. It is roughly 1/3 of the peak to peak, so the actually ceramic capacitance required would be lower.
This capacitance will operate the electrolytic capacitor at 1/2 it's rated RMS current or 1/4 its rated power dissipation, which is safe, but will still feel warm. (A 125C rated capacitor would be rated for 100C temperature rise. At 1/4 power dissipation, it's still operating at 25C temperture rise or 50C temperature)
C= (I * Vo) / (deltaV * Vin * fs) = (6A * 12V) / (60mV * 18V * 300kHz) = 222µF
2 x 220µF (electrolytic, Panasonic EEEFK1H221P) as bulk capacitors.
2 x 4.7µF (ceramic at the power stage (murata, GRM32ER71H475KA88L) in power stage.
Is it right? Do you have other suggestion?
But regarding temperature problem, I found out why the caps are going warm. Both electrolytic caps are located near to high side FET. The high side FET produce a heat above 80°C and the PCB are going warm. It was the main reason for the problem. In new re-layout I will use a new place for the caps.
Other questions:
1) The TPS40k Loop Stability tool: It seems to be an interesting tool and I tried to use this Excel file but if I enter any data in green cells, I get no results. The Analysis Toolpak is selected. What is the problem?
2) Output voltage: I have approximately 6.7V at output, if no load is connected. If I connect a 560 ohm resistor at the output, then the output voltage is approximately 12V. But do you mean, is this solution the right way or I must change the resistor divider from network compensation?
Best regards, Bizhan Behrouz
I'm not certain what the problem is, but here are some possible actions to check:
1) Check to see if the data you are entering is in the form of a non-zero number. Many values are used in the denominator of calculations and zero values result in errors. If you are trying to use zero current, look at your feedback dividier and calclate the feedback divider current, which appears as a load.
2) Do not enter units into the datafields. Excel sees these as text and will not be able to perform math functions on them
3) Verify "Analysis Tool Pack is "checked" under Tools > Add-Ins
If none of those work, enter your data into the tool, save it and then attach it a reply to this forum post and I will take a look at it. You can attach files using the "Options" tab at the top of the compose page (Compose / Options / Preview) or using the Insert Media icon (This is the second to last icon from the Right in the bottom row of icons at the top of the Compose text box. It looks like a filmstrip with a + symbol) The Insert Media icon can be used to insert multiple files of any file type into a post. If it is a recognized graphic format, it will be displayed. Other files types appear as clickable links.
Try placing an oscilloscope probe on the output voltage, I suspect that you have a loop staibility issue at very light loading conditions in discontinuous conduction mode due to the TPS40054's diode emulation. You could try backing off the control loop gain a little for some more stability under this condition, you could add a pre-load if the impact on efficiency is acceptable or you could even reduce the feedback divider component values so the feedback divider sinks enough current to maintain stability.
It is also possible that at very light loading conditions there is insufficient low-side MOSFET conduction time to recharge the bootstrap diode and the high-side gate drive is dropping out under very light loads. This can be improved by placing an external diode from BP10 to BOOST to provide a better current path to recharge the bootstrap capacitor.
Dear Peter,
1) Regarding Loop Stability tool, please check the attached file. You can see my data. I’m not sure but I think that the Excel file has a bug.
2) Other question: Calculate the snubber components:
The SwitcherPro circuit uses a resistor and capacitor between Drain and Source of synchronous rectifier. I couldn’t find any information about these components in data sheet of TPS40054. But I found some information about snubber in TI forum and I made a summary. Please check the attacked file and give me your feed back that my summery is correct.
Bizhan
Bizhan,
I've attached a screen shot of the file you sent me. It is calculating component values and generating graphs as it is intended when I open it. I am not sure why you are having an issue. Could you take a screen shot of the file when you have it open so I can see what error you are having?
Regarding your snubber summery, everything is correct.
Equation 3a and 3b will simplify to: C + Cp = 4Cp or Cp = 1/3 * C
This will help you solve for Cp and Lsl more easily.
I use Excel 2003 German. I have checked the problem with other versions of Excel. Here is the result:
- It doesn’t work with Excel 2003 German.
It works with Excel 2007 German. But after opening the file, Excel tries to repair it. You get the same result with original file of TI.
- It works with Excel 2003 English.
I’m not sure but I think that it’s a bug in the original file. I will use Excel 2007 and it’s ok.
Best regards, Behrouz
Behrouz,
I am afraid I don't read German, but I asked one of my German counter parts to read the error message and suspect that the issue is a conflict between the script functions and macros used in the spreadsheet and the security settings in the German Excel 2003. Check your security settings in Excel and see if they are set to allow VBA and ActiveX script execution
I have calculated the RA and CA on the page 10 of data sheet. The value of RA is dependent on RKFF and VIN(min) and the value of CA is dependent on RA and fSW. Is it right?
SwicherPro always calculates 243kohm and 470pF. But I don’t know why. Is it normal?
Thank you!
Equation 4 for CA on page 10 of the datasheet has an error.
7.9 should be (8.0 - 7.9)
The equation should be CA = I * t / DV
I is the current (8V - 3.48V) / RA
t is the time 1/fSW
DV is the allowable voltage change on CA