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Non-Isolated DC/DC Forum
Output Capacitor of TPS51124
Output capacitor of TPS51124 (or TPS51125, TPS51218) are designed to satisfy the stability and the ripple voltage as in the data sheet.
In layout, if we add some small bypass capacitors in parallel with the output capacitor to filter the high frequency components, would you please recommend the
1. will bypass capacitors affect the stability and the ripple voltage of the circuit?
2. If yes, should we calculate again the new value of capacitance and ESR of the output capacitor? And how can we calculate those values?
Thank you very much for your help.
Yes, paralleling small ceramic (or other types of capacitors) in parallel with larger capacitance capacitors changes the impedance of the output capacitor and will affect the response of the loop and will affect the ripple. This is true for any regulator but is especially important for DCAP and other hysteretic type topologies that require ripple to regulate.
The math to determine the new impedance is complicated and there is no exact equation that I can give to guarantee stability, etc. At a minimum, I would recommend keeping the capacitance of the ceramics less than 5% (the lower the better) of the sum of the other, higher ESR caps.
I recommend simulating the new capacitor bank in spice and seeing if its impedance is significantly different than without the smaller ceramics. If not, then it is likely ok to add the extra caps. I would highly recommend testing the proposed output cap bank on the EVM before going to production.
Thank you very much for your reply. I appreciate that.
Although it too late to response on your threads, but I had same problem with resulting ESR of many outputs capacitors (in most case 3 capacitors, with different C and ERS).
as written above there is no simple equation to calculate the resulting capacitance and resulting ESR, but you need the resulting ESR to design the compensation network. In most case you have to write also design specification demanded by customers. Here is my method,
resulting capacitance = sum of all in parallel
to calculate the ESR, first forget the capacitors which capacitance is less than 10% of highest one.
-if rest have same capacitance and ESR, then you can just calculate the resulting ESR as parallel resistance.
-if the capacitors have different capacitance and ESR, just simulate it with e.g 1k resistance in series to parallel output capacitors(input signal on 1k n Cout, output at Cout).
let TINA to simulate/draw the Ac characteristics!
First zero is important for compensation network design.
How you can find frequency where first zero occurs?
The first zero is at the frequency (fz)where the phase increased by 45° after phase valley.
Resulting ESR = 1/(2*pi*(sum of all c)). There are other zeros at higher frequencies which are not important.
you can go further design with this resulting ESR.
Remark: there are many zero/pole/zero/pole ... in case parallel capacitors, which is also written by John in another threads.
TPS51124 has been transferred to Japan application team. If you have any question about this part. Please contact Shuichi Ishikawa (firstname.lastname@example.org) directly.
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