I like to use LM5030 Current Mode Control PWM Controller in push-pull configuration with fixed PWM duty cycle.
With this configuration, if VFB pin is tied to GND and COMP pin left open (without loop compenstaion network implemented), will it have any problem in fucntionality of IC?
Is this configuration adviceable? or loop compensation network is mandatory?If this above mentioned configuration is acceptable what are all the additional point to be taken care in design?.
Yes you can run the LM5030 open loop by grounding the VFB pin. I recommend that you add a 1nF cap from the COMP pin to ground for noise.
Thanks for the reply. Kindly clarify the following queries.
1. What is the recommended value of capacitor at SS (soft start) pin of LM5030 and how to calculate soft start time period?
2. I am planning to power LM5030 from main supply used for push-pull transformer. Once auxiliary winding is energized, secondary circuit will power LM5030 IC.
If so, how to calculate the startup resistor to provided at VIN pin?. Is there any other specific consideration to be taken care?.
Thanks in advance.
Also please clarify, what will be frequency to be considered for current sense input RC filter calculation. Let oscillator frequency is 25KHz.
1-SS is really application dependent, as the power supply starts up there is a large inrush current as the output capacitors are charged up from zero volts. A reasonable start point is be 3-5 ms. The PWM has a 1.4V offset, so there will be no OUT1 or OUT2 drive pulses until the SS voltage is > 1.4V. SS time= Css XV/Iss, iss is 10uA typical, start out with a SS capacitor of 0.033uF.
2-Typically we use 10 ohms.
Keep the RC time constant of the filter > 10X the oscillator frequency.
I have another query in LM5030 PWM controller.
I am planning to synchronize three LM5030 PWM controller with an external clock of pulse width 50nsec.
In data sheet it is given as the minimum threshold for SYNC clock is 3V.
I am generating SYNC clock in CPLD and isolated by an opto coupler. Whether i can use VCC (10V) supply of LM5030 to pull up resistor.
What is the max acceptable amplitude of SYNC clock at RT pin?.
Kindly clarify the same.
The maximum voltage that can be applied to the RT pin is specified in the Maximum Rating Table in the Data Sheet, it is 5.5V.
In continuation with the above, i need clarification on synchronizing the operation of three LM5030 PWM controller.
I am operating three PWM controller at same frequency of 50KHz. I want to synchronize the operation of all the three controller with an external SYNC clock at RT pin.
It is recommended that the external SYNC clock is to be capacitively coupled to RT pin through 100pF. (Resistor shown in figure is not actual value).
1) Whether one PWM controller act as Master and others as slave?. Is series capacitor and RT sufficient for one PWM controller?
2) Individual PWM controllers are to be connected to a common SYNC clock?
My understanding of configuration is shown in figure.
Which configuration is correct for synchronizing the operation of PWM Controller?
Use scheme-1 make sure the SYNC pulse width is between 50ns and 150ns max.
The RT pin is regulated to 2.0V, which establishes the oscillator current. A positive SYNC pulse (> 3.8V) at the RT pin triggers an internal comparator, synchronizing the oscillators to an external CLK. When a sync pulse width larger than 150ns is applied to RT/SYNC pin the bias point of the RT pin is disrupted which decreases the DC current into the RT pin this will change the oscillator frequency.
what will be the minimum oscillator frequency that can be achievable by RT resistor?. I am planning to operate at 50KHz.
Is there any calculation sheet for compensation network tuning?
It should be ok to run the oscillator at 50kHz. The things to be aware of is that as the oscillator current get smaller the noise susceptibility increase, so be careful with the printed circuit board layout. Follow the guidelines in the data sheet. No there is no calculation sheet for the compensation network.
In Frequency Vs RT resistor characteristic,the graph is shown for 100KHz to 1000KHz.
Is there any extended graph for for lower frequency upto 10KHz oscillator frequency?
As you pointed out in your previous reply, the external pulse width should be 15 to 150nsec and it is given in data sheet as "The external clock must be of higher frequency than the frequency set by RT resistor".
What is the allowable external clock frequency range?
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No there is no frequency vs RT graph available below 100kHz. When you operate at lower frequency, the oscillator current gets smaller, and as a result the oscillator is more susceptible to noise. You should be able to operate down to 50kHz, but follow the data sheet guide line for the PWB layout.
Thanks for your immediately reply.
What should be external synchronization clock frequency for 50KHz internal oscillator frequency?
Let pulse width of SYNC clock be at 75nsec.
Awaiting for your reply.
The sync clock should be 10-20% than the 50kHz oscillator, yes a pulse width of 75nsec will work.
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