TPS40077 / voltage ripple(rising) after start up

Yaita-san,

Can you post the schematic? Where is the source of the PGD pullup? How much current does PGD-low draw?

Have them measure LVBP at the same time to see if that is where the glitch is coming from.

Regards,

MC.

Yaita-san,

There is another possibility with the 40077. This device has predictive dead time delay, and when the predictive dead time delay is in effect the dead time is less than about 10nSec. However, when the device is going through soft start, the predictive dead time delay is disabled and the dead time is fixed at about 80nSec.

When the device is finished soft start, it transitions from fixed dead time to predictive dead time, and that causes a slight change in transfer function. At the transition, the duty cycle will be a bit too high because the pulse width increases by the difference of about 70nSec. At that point the control loop has to re-adjust the duty downwards to compensate.

Please have them take a high resolution snapshot right as the transition (glitch) occurs. They can probably use the PGD signal as a scope trigger. The picture should be at a timebase that just covers the transition area, and then they can zoom in to the individual cycles to see if they can see the transition in dead time.

If this proves to be the cause of the bump in the output, they can mitigate the amplitude of the bump with a faster loop compensation, and also higher value output capacitance.

Regards,

MC.

Yaita-san,

The device uses predictive dead time delay on both edges. In the transition from SW-low to SW-high, the device detects LFET body diode conduction by looking for -VE voltage at SW. On the other edge SW-high to SW-low, the device looks at SW and LDRV and avoids them both being high at the same time.

For the SW-low to SW-high edge, using an LFET that is slower will help. This is because with a slower LFET, the resulting dead time adjustment from fixed 80nSec to predictive delay will be reduced. For example, it may transition from a fixed 80nSec to a predictive 70nSec, and the delta is small. If the LFET is very fast, it may need to adjust from 80nSec to 10nSec which results in a bigger delta and a bigger volt-second change applied to the choke. Also for the same edge, using an LFET with a lower body diode forward voltage will help, but only a bit. This is because as the device transitions from a fixed 80nSec to "almost no body diode conduction", there are less volt-seconds that are added to the inductor voltage with the loss of the body diode time.

On the other edge SW-high to SW-low, also using a slower LFET and a slower HFET will help, for the same reasons. The dead time adjustment delta will be smaller. The body diode voltage does not come into play on this edge.

TI FETs, the NexFETs, will help with the body diode effect. They have a body diode drop that is a bit smaller than other vendors, but again this effect will be minimal.

NexFETs are not slow, they are extremely fast. So just swapping the FETs out with NexFETs will make the glitch bigger. If they do go with NexFETs, they will need to add small-value (≈ 2 to 10Ω) gate resistors to both FETs to slow them down. But this is actually good because they will have control on the effect by adjusting the gate resistor value to get improvement. If they use inherently slow FETs, they have no control over the phenomenon.

They should be able to get improvement by designing the loop compensation to be faster, if that is possible. And increasing the output capacitance will also help.

Regards,

MC.

Yaita-san,

Martin is out of the office at the moment, so he has asked me to help you with your issue.

This does not appear to be a typical start-up, so it will require some additional analysis to determine the likely cause.

If it's possible to capture this "Glitch" with the following additional waveforms, and hopefully at a higher time-resolution:

Set One: VOUT, VIN, SS and SW

Set Two: VOUT, SS, FB and BOOST 

Please set the scope for 5us / division with a Single Sequence trigger on the VOUT channel rising above 1.02V so that we can check the main control signals that would be affecting the ouptut voltage at this point.  I'm looking for a reason the duty cycle might suddenly change

In addition, can you check the RT and KFF resistors to see if the part may be operating very near UVLO and VDD is drooping?