• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 63 subscribers
  • Views 596 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS54240 method of ditering circuit

Mike, Jung
Prodigy 230 points
Other Parts Discussed in Thread: TPS54240, TPS54340

Dear all.

My customer strongly want to apply to dithering circuit at TPS54240.

they exclude the possibility of other method such as snubber ane etc.

so, I search the app. note(SLUA646).

is it possible to apply the tps54240?

if not, can you please give me some information on how to handle the work?

Thanks & best regards.

  • 0
    TI__Guru**** 191445 points

    You might be able to do that.  I have not tested directly with TPS54240, but I have tried some FM modulation with similar PLL type clock synchronization.  The PLL will track well up to about +/- 5 kHz frequency change. Between about 5 kHz and 10 kHz, the frequency is maintained but the phase is not locked.  Above 1- kHz deviation, the PLL cannot track.  This was just an informal test.  I do not have any data for it.

  • 0 in reply to JohnTucker
    TI__Mastermind 35115 points

    I tested this circuit out with the TPS54340 RT/CLK pin and it worked well. The TPS54240 uses the same RT/CLK circuit so it should work. Just make sure to limit the length of connections to the RT/CLK pin to avoid extra jitter in the switching frequeny. C2 and R5 from the application note should be placed right next to the RT/CLK pin.