LM2841x design shown negative phase margin at minimum voltage

Hi Sanjib,

If you try changing the output capacitor to one that has a lower ESR, the phase margin improves. I used the AVX cap at 33uF, 0.6mohm in the alternate component list and the phase margin is much better.

Let me know if you can get these results. I can share my design with you.

Just curious...why would webench pick that capacitor in the first place?

Hi Kevin,

Thank you for your fast response!

I am observing that is rather the opposite of what you have mentioned. I am observing and output capacitor with a higher ESR is giving better phase margin. The output capacitor I chose 22uF, 0.2 mohm, which gives 26.9deg at VIN = 24V and (-8deg) at VIN = 5V;

I believe the 33uF capacitor you have mentioned has ESR = 0.6ohm and not 0.6mohm; I could not find any such cap from the list Webench has provided for this design. Even if I use 33uF & 0.6mohm to make a custom part, that gives:

26.4 deg phase margin @ VIN = 24V

(-4.4deg) phase margin @ VIN = 5V

Regards,

Sanjib   

Hi Sanjib,

I was mistaken - the output capacitor mentioned was 0.6ohm, not 0.6mohms.

I think the results you gave above are for a different capacitor. Perhaps you adjusted the Optimizer knob, which would run the BOM selection algorithm again and select a new set of BOM components.

The BOM selection algorithm right now does not optimize for phase margin on this part, which is why you are seeing these results by default.

Hi Kevin,

Please note that I did not optimize.

I have actually selected an output capacitor by clicking on the EDIT button for the output capacitor and selecting one from the list which has the best ESR (22uF, 2mohm), because the output ripple requirement is very tight.

My major concerns are:

1. The tool does not throw warning for the worst case phase margin, which is at the lowest VIN (4.5V in my case); Since at max input voltage, i.e. VIN = 40V the phase margin is just above 35deg, it does not throw warning, but when I calculate the phase margin for VIN = 4.5V, I see it is < 0deg.

2. If the capacitor 22uF, ESR = 2mohm gives <0deg phase margin at the lower VIN range, which is input to the Webench design, the tool should not have listed that in the alternative parts for the Cout.

3. Even though the phase margin is <0deg at VIN = 4.5V, the circuit is working fine at VIN = 4.5V in the lab when it is actually implemented. Theoretically the design is unstable for this condition and should not have worked. Any reason why? Should we trust the Webench calculated phase margin? 

Regards,

Sanjib

I would really like to see an answer for this also.  is there any chance you can measure the loop response at different input voltages?

Hi Sanjib,

I follow how you selected the Cout and got the results that you did.

For points #1 and #2, I hear your concerns about the tool looking only at the VinMax value for the design when checking the phase margin. I will bring these concerns to the group to see how we can address this at the system level.

For point #3, from what I understand the calculated values for phase margin and xover frequecy used in Op Vals are from a control loop model, with parameters specific to this IC. There may be discrepancies between the results these equations used, the SPICE simulation results, and the actual device.

Hi Kevin,

Any further action taken on the phase margin issue? Any plans for looking into this?

Regards,

Sanjib

Hi Sanjib,

Thank you for the follow-up. Yes, we are looking into this phase margin calculation across the input voltages, but it may not be an immediate fix.