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TPS54060 design: Improving phase margin

Other Parts Discussed in Thread: TPS54060

Hello,

I am designing a power supply with the following spec:

VIN = 4.2V to 50V

VOUT = 3.3V; LOAD = 200mA

I am using TPS54060 for this and Webench has suggested the attached design; I have chosen a capacitor with lowest values for capacitance & ESR from the suggested list of capacitors for this design. 

4745.webench_design_670735_18_903927795.pdf

As I have to keep the output ripple to minimum, I would need to choose Cout with minimum ESR. With the current Cout, the phase margin is 37deg @ VIN = 50V; The phase margin is ~22degC at the lowest VIN. How could I improve that other than by increasing the Cout value?

Regards,

Sanjib

 

  • Hi Sanjib

    For I can not see your attached picture, I will give you a suggestion to improve the circuit phase.

    You could find the simplified schematic of the device(page 1), and the VSENSE PIN is feedback pin, so you can add a capacitor between Vout and VSENSE to do phase lead compensation, the value of the capacitor is according to your circuit.

    Best Regards

    Feng Zhao

  • Hi Feng,

    Thanks for your response!

    I have attached the PDF report of the design now in my previous post. You should be able to see the design now.

    Can I add this in the Webench and re-do the calculation? Please suggest.

    Regards,

    Sanjib

  • Webench does not have the capability to add any feed forward capacitance for TPS54060.  You are already using an output capacitor with 28 mohm ESR that produces an ESR zero at 121 kHz.  When I run the simulation from the same inputs, I get 48.6 deg. PM, not 37.6 deg.  Webench is not very useful for optimizing designs.  You pretty much have to use whatever it puts out.  The WB team is starting to roll out some better tools for optimizing compensation, but TPS54060 is not supported yet.  I would recommend using the pspice average model to optimize your compensation.  It is totally flexible and will support feed forward capacitor.