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TPS50601-SP

Hello TI,

In the datasheet of the TPS50601, it states in the following attachment.

 

4087.TPS50601-SP.docx

 

I wanted clarification on this.  Why is it necessary to use an inverter specifically?  Why not just a buffer?  

Thanks,

Dan

  • Hello TI, 

    Additional question:

    I had another question, this one regarding the EN pin.  I would like to utilize the EN pin to monitor two separate voltages as shown below.  This way, both the 5V input as well as the 3.3V from the upper regulator needs to be present in order to enable the lower regulator.  I am doing this as sort of a sequencing mechanism for the 3.3V and 1.5V.  I see the equations 4 and 5 in the datasheet that call out the R1 and R2 values when monitoring a single voltage, but could you let me know the equations if monitoring two voltages as shown below?  I can figure it out, but not sure about the Ih hysteresis current.  Does the Ih current become active when the EN pin crosses below the threshold, or is it become active when it goes above the threshold?  The datasheet doesn’t say.

     5635.TPS50601 Schematic.docx

    Also, any drawbacks or concerns electrically to doing it this way?  I am essentially OR’ing the enable function from two voltages.  Seems like this should be doable but wanted to make sure.

  • Is anyone at TI going to address this?

  • I'll see if I can track someone down to answer this.  It may take a few days as we are going into the week end.

  • Dan,

                If you are only using one POL and want to synchronize externally to frequency,  then you only need a buffer.  However if you have two POLs and want to synchronize the frequency externally then you need one buffer and one inverter this will allow you to put one POL out of phase with the 2nd POL.

              

         See the schematic in the users manual  under technical documents for both single EVM as well as Dual EVM.   

    http://www.ti.com/tool/TPS50601SPEVM-D?keyMatch=tps50601&tisearch=Search-EN#Technical Documents

  • Dan,

           I will look into it and respond to your question.

  • Hello TI,

    Thanks, this answers my first question.  Do you have an answer on the second question about the EN pin?

  • Hello TI,

    This is still an open post as my second question has not been answer on the EN pin.

    Here's another one too:

    .  What is the typical failure mode when the input voltage exceeds the rated.  Does the output typically go to the input rail due to a failure of the internal MOSFET?  Or does the output simply go to 0?

    Thanks,

    Dan

  • Dan,

      Regarding your question on EN pin I am investigating and will provide you input on that.

     Regarding typical failiiure mode MOSFET will fail short intitillay an if the failure conditon persists ( ie. if there is no external secondary protection) then the the short short propagates and often bond wires will open, resulting in Mosfet being open.