Hello,
We consider to adding the SBD to between L1 and PGND and between L2 and Vout for reducing the power loss during dead time.
Could you please let me know if there are any concern?
Best Regards,
Ryuji Asaka
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Hello,
We consider to adding the SBD to between L1 and PGND and between L2 and Vout for reducing the power loss during dead time.
Could you please let me know if there are any concern?
Best Regards,
Ryuji Asaka
Ryuji-san,
what do you mean with SBD?
-Florian
I'd strongly recommend not adding the diodes in your sketch.
Basically you get the diodes due to the back-gate diodes of the internal switches anyway. The first one comes with the low-side-switch transistor between L1 and GND. The second with the high-side-switch of the transistor between L2 and VOUT.
What kind of technical problem do you like to adress?
Hello Florian san,
I think that we can reduce the power loss by adding the diodes.
Please see the below datasheet P.18.
http://www.ti.com/lit/ds/symlink/lm20333.pdf
I think that this method is not special method for improvement efficiency.
Could you please recheck ?
Best Regards,
Ryuji Asaka
Hi Ryuji-san,
well, you can slightly reduce the peaks in the back-gate-time as you are plan to use schottky's.
On the other hand you add capacitance to the SW Nodes, which does not help you. The LM20333 has a switching frequency of 250kHz to 1.5MHz, and this datasheet also claims that it can help at some conditions.
I double-checked your circuit with the design team: you can use the circuit if you think it helps in your application.
Regards,
Florian