LM5118 boost ratio

Hello John,

Can you provide the specifications for the converter (VIN Range, VOUT, Switching Frequency, Max Load…), and possibly a schematic?

Are you just seeing the issue just at maximum load or all loading conditions? What VIN range are you seeing the part work properly? 

 

Thanks,

Garrett

Hi Garrett,

A situation when the output seems to be unable to keep up is:

Fsw = ~500kHz
Vin = ~20V through a total source resistance of ~1 ohm
Vout = ~21V
Load = ~3.5A

The load where it occurs depends on Vin.  At higher Vin, it can handle a higher load.  At lower loads, it can handle a lower Vin.  From what I can gather, the switches are turning on fine, and the UVLO function or current limit are not causing the output to fall either.

It seems like a tipping point is reached when the combination of low Vin and high load bring down the input voltage at the IC pin, such that there is no longer enough voltage across the inductor to ramp/charge up the inductor sufficiently during the switch on time.  Peak inductor current itself is likely also being limited by the source resistance.  

I suppose two of the only ways to allow for a higher load and/or lower voltage (depending on their combination as described above) are to decrease source resistance or decrease the switching frequency (to give the switches more on time to charge the inductor).  From my calculations, changing the inductor value itself would have little to no effect on preventing this.

Thanks,

John

John,

Have you check to ensure that the duty cycle matches with the voltage seen at the VIN pin? I’m thinking that the chosen ramp capacitor value maybe too small, giving a lower than expected on time resulting in an unregulated output. The calculation for the ramp capacitor can be found on page 27 of the datasheet.

Your design should be based on the voltage seen at the VIN pin due to the emulated current mode operation of the LM5118. Here is the link to the quick start calculator for fast calculations.

 http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=snvu065&fileType=zip

Thanks,

Garrett

Garrett,

Thanks for this info.  I actually appear to be seeing a higher duty cycle than expected, based on the calculations in the datasheet.  And, while the output is ramping down, the off time is within the allowable range shown in the datasheet for minimum off time, so does appear to be trying to drive the output as strongly as possible.

You still raise a good point about the ramp capacitor.  My ramp capacitor is too small according to the calculations.  It is confusing, though, that if that calculation is meant to provide a minimum required capacitance, the chosen value in the datasheet design example is below that calculated value (granted, it's just slightly below).  I don't think I realized before that that was a hard minimum.

How important is it to satisfy that minimum capacitance?  Is there already some margin built into that calculation?  Are there other things that can occur with a ramp capacitor being too small?  At what point does that capacitor become too big?

Thanks

John,

 The calculation for the ramp capacitor is based on emulating the inductor current and adding slope compensation. The closer to the calculated value the actual ramp capacitor is the more accurately the inductor current is emulated. Too small and the converter can have too much slope compensation. Too large a cap and there will not be enough slope compensation resulting in sub harmonic oscillation.

 Can you post any waveforms and a schematic? Both of the switch pins and inductor current. I think that may aid in resolving the issue.

 

Thanks,

 Garrett

Hi Garrett,
Pardon the long delay and subject change. My ability to provide a schematic and/or waveforms is somewhat limited, but at any rate, I found that I had excessive source resistance in my setup, so this issue has gone away. However, I am running into a different issue (but perhaps somewhat related) that is unsettling.

At lower Vin's and high loads (for example, the Vin/Iout parameters I indicated in a previous message in this thread), the average output voltage level is dropping lower than the nominal, by up to a few hundred mV or so. It seems to start happening when the circuit is in transition mode and close to full-buck boost mode (i.e., Vin ~24.5V, boost duty cycle ~45%, buck duty cycle ~60%). The output has dropped by most of the few hundred mV range by the time full buck-boost mode is reached (Vin ~23.5V). It continues to drop some more as Vin is lowered further down past Vout, but most of the dropping seems to correspond to the range described above.

The puzzling thing is my circuit exhibits this drop while its configuration is very similar to a modified demo board circuit (i.e., I modified the demo board to accommodate the output voltage and switching frequency and related compensation components) that does not show this behavior.

I have a lower Rs value, different FETs (do have higher Rds, but still quite small), and different diodes (slightly larger Vf, but still are schottkys like the demo board) than the demo board. The lower Rs calls for a larger Cramp per the calculations, but whether I use the same cap value as the demo board or go closer to the newly calculated value, I still get similar results. I also still see a drop, although not as large, when using a very large Cramp, but as one would expect, sub-harmonic oscillation becomes problematic.

Pardon me, this is a lot of information, and likely a difficult problem for someone to diagnose from afar, but do you have any suggestions on what could be causing this sort of behavior?


I suspected a problem in my circuit’s layout where perhaps the node feeding the FB pin resistor divider circuit had more voltage drop than the actual output of the whole circuit, but I’ve been able to rule that out as a cause. Also, my Chb (to use the name from the quick calcs spreadsheet) value is too small for the FET gate charge (according to that spreadsheet), but I increased that to a larger value with no noticeable change to the output behavior. The demo board Chb value appears to be undersized as well, so it’s no surprise this didn’t have an effect.

One remaining relevant observation I have is that I see that the layout in the demo board uses plane shapes for each main node of the circuit (Vin, SW1, SW2, and Vout), while my circuit’s layout makes more frequent use of thick traces instead of plane shapes. Would additional IR drops in that sort of layout (and/or increased voltage drops due to using different FETs or Diodes) between the Vin and Vout nodes cause the output to drop in buck-boost mode at higher loads (or would it just decrease efficiency)? This seems a possibility since the emulated current ramp appears to not depend at all on Vout in Buck Boost mode.

Thanks

John,

First, are you still switching at 500kHz? Also, just to clarify you modified the evaluation board to meet you design and you didn’t see Vout drop as described above? If that’s correct, it seems to point toward there being a layout issue with your board. For buck-boost and transition modes the IR drops become greater because of the increased average inductor current as compared to buck mode. This will impact efficiency more so than output regulation. Try revising your layout based on the evaluation board and the layout guidelines in the datasheet.

Thanks,

Garrett,

Thanks for the reply. To answer your questions…Yes, I'm still switching at 500kHz. And your clarification is accurate, that I don't see the Vout drop when adjusting the demo board to my Vout, switching frequency, and applicable compensation network adjustments.


The voltage drops across traces/planes are small in comparison to the drops across the series components, both in the case of the demo board and my board (granted, in my board, both sources of voltage drop are larger than the demo board). Let’s assume a high inductor current of ~10A when using a low Vin and high load. I’m assuming the plane resistances in the demo board are in the low single digit milliohm range. Per the datasheets, the FETs’ Rds values are a little over 10mohms each, the inductor adds a very small of DCR (<2mohms) as well, and the Diode drops are ~.5 to .54V each at 10A at room temperature. At 10A inductor current, I have more than .1V of IR drop in the components.

In contrast (but also as a point of comparison), upon further examination, my overall total trace resistance Vin to Vout is approximately 15mohms, but my other components add much more drop. My FETs have ~40mohms of Rds, my inductor has a DCR of ~11mohms, and my diode drops are ~.63V each at 10A at room temperature.

So, it seems like there is significantly more additional drop in components than traces in my board, but regardless, it all seems to add up to an excessive amount of additional IR drop to be able to explain a drop of only 200 to 300mV or so on the output. I don’t believe I can rely on being able to switch to the same components used on the demo boards, or find suitable parts that have similarly very low resistances, etc.

I do also use different input and output capacitance, but that shouldn’t have an effect on the average/DC level of Vout.

Pardon my beating a dead horse here, but at this point, is changing the layout (or parts) the only viable mitigating step going forward that you can think of? Despite all the additional drops, I would agree with you that IR drops would impact efficiency more so than output regulation, which helps make this more unsettling. The emulated current ramp only depending on Vin during buck boost mode doesn’t seem to matter because my duty cycle appears fine (if anything, a little larger than expected) when looking at the Vin pin of the IC.

Thanks.


PS - As a side note, the layout guidelines in the datasheet (not counting the example layout that got added in August which seems to align with the demo board) put emphasis on the area covered by the switching current loops. I have put a significant emphasis on that and have switches and diodes co-located on opposite sides of the board to help decrease the area. But doing that makes plane shapes harder to utilize as interconnects. The demo board/example layout use plane shapes, but the areas covered by those current loops are larger. Since the areas of those current paths are OK on the demo board, I will try to move towards a layout more resembling that. Also, while I still feel I’ve likely ruled out the issue where the point of the circuit feeding the FB pin resistor divider has a higher voltage (I implied a lower voltage by mistake in the previous post) than the actual output point of the whole circuit, I will also try to make the actual output point of the whole circuit be the same point that feeds the FB resistor divider as is done in the demo board. (I use the word “point” because I’m referring to specific parts of the same electrical node)

John,

Yes I think the issue is layout related. One other area to look is at your current sense resistor path to the chip. Is it kelvin connected? If not I’m thinking that there could be noise causing the part to cycle to cycle current limit for a few cycles but not for enough (< 256 cycles) to enter hiccup mode. This would align with seeing a small VOUT drop at higher loads in buck-boost and transition mode due to having higher inductor currents.

Thanks,

Thanks, Garrett.

Are you also saying you think it probably wouldn't be related to parts selection either?

To answer your question, yes, it is Kelvin connected, and it's also almost 20% smaller than the value specified in the quick calcs spreadsheet.

Would cycle to cycle current limit be indicated by the switch on time being randomly significantly smaller than normal? I actually thought I saw that for both boards (which is one reason it's probably not related) in transition mode, while I was ramping down the input voltage, and figured it was subharmonic oscillation that I couldn't really do anything about since the ramp capacitor was already smaller than the calculations called for.

Thanks.

Thanks, Garrett.

I will test with additional bulk capacitance and let you know. Since the FETs, etc on the demo board are difference, I will still keep parts selection in mind if the extra capacitance and layout don't fix the issue. Thanks for the additional current limit/noise info as well.

Garrett,

Per your request to let you know - I increased the capacitance to approximately the same total that is used on the demo board, and did not observe an improvement to the issue. Thanks though. It was definitely worth a try.

Thanks