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TPS61230DRC Thermal Pad Issue

I am facing PCB thermal pad design issue in TPS61230DRC.
Issue is if we place via’s on thermal pad, via’s will suck all solder during re-flow soldering.

Please suggest for required changes to resolve this issue

  • this could happen if the vias and stencil is not good designed. it also relate to the board assemble site. please refer this application note SLOA120 and datasheet page 30 for the thermal pad vias design.

    and external via outside the pad is also another solution.

    thanks

    Jasper

  • Hi Jasper,

    Thank you for your reply,

    Look both image and my comment in red.

    External via option rule out because of keepout area restriction in this IC see below image.

    Then second option is plugged via which will increase PCB cost ?

    Is there any other work around ?

     



  • the via can be placed beside the keep out area. it can still help the thermal performance although may not as good as right under the pad.
    what is the hole size in your real board? these via should not be larger enough and sink more of the solder, maybe just a little.

    may i know your electrical input and output condition?

    thanks
    Jasper Li
  • Hello Jasper

    Thank you for your reply.

    The customer is using this part to boost Li-ion battery input to 5V, 1A continuous and 2A transient load.

    As mentioned in the land pattern data on datasheet page 30, the customer has incorporated 0.2mm dia vias at the Power Pad.

    The assembly site has informed the customer that there may be a case of percolation of solder to bottom layers during reflow soldering, hence they wish to confirm if keeping via dia as 0.2mm takes care of this concern.

    Further, if you could suggest any points to take care of particularly, to ensure similar problem doesn't arise during reflow soldering, would be a great help!

    Thanks in advance for your help on this issue.

    Regards,
  • hi BHARAT

    The pattern in datasheet is for reference. i would suggest customer to check with the assemble site the acceptable via size. 

    Thanks

    Jasper Li