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TPS65400 Layout Example Notes & Errors

Other Parts Discussed in Thread: TPS65400

Hi all,

in the process of debugging the TPS65400 board that I designed (e2e.ti.com/.../435181) I came across some incongruences/errors in the documentation of the component.

Starting with what IMHO are errors:


- PIN 40/41 are both marked as I2C_ALERT while pin 40 should be RCLOCK_SYNC;

- SDA, SCL and VDDD have all a via that connects them to GND according to the vias description, if the via will only represent a connection to a signal plane where the routing is done this notation should also be applied to CLK_OUT, I2C_ALERT, RST_N, ENSWx, CE.

I think it is also misleading how the signal ground and power ground are treated in different pictures. Let consider figure 6, here the SGND and PGND are kept separated and only connected together in one point which probably should be between the pin 21 (AGND) and the thermal pad of the component (this connection is mentioned in 11.1 Layout Guidelines) but Figure 11.2 considers all the GNDs like the same. It might be worthy to separte GNDs also in Figure 11.2 , unless all the AGND referenced signal in the top section of figure 11.2 can be safely connected directly to the power GND of the thermal pad.
Regards,

Simone

  • Hi Simone,

    I have checked the data sheet, we may have some error in layout picture. SDA, SCL and VDDD pin should not have VIA to GND. we will try to update the DS.
    For the AGND and PGND, it should be ok to connect those two GND together. TPS65400 is much rubust, don't need to connect AGND to PGND in one point, also it's diffcult for customer to connect in one point in their PCB layout.
    let me know if you have any more question.
    thanks!
    Eric