On my board, the LDRV and HDRV signals are both on at the same time as shown in the screen shot below. Channel 1 is HDRV, and channel 2 is LDRV. The data sheet is pretty clear that LDRV supposed to rise 65ns after HDRV falls. They are never supposed to be high at the same time. Is this a bug in the chip, or is there something I can do to fix this problem?
The other half of the cycle seems to work OK, with HDRV rising about 40nS after LDRV is low. This is not the 65nS specified in the data sheet, but at least there is a dead time.
Also the LDRV rise time seems slow. The FET gate capacitance is about 3300pF which is fairly typical.
