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TPS5430 application questions

Other Parts Discussed in Thread: TPS5430

Hi,

As below,this is the description in TPS5430 datasheet:

Due to the internal design of the TPS543x, there are both upper and lower output voltage limits for any given
input voltage. The upper limit of the output voltage set point is constrained by the maximum duty cycle of 87%
and is given by:
VOUTMAX= 0.87x((VINMIN-IOMAX0.230)+VD)-(IOMAXRL)-VD         (13)
Where
VINMIN = minimum input voltage
IOMAX = maximum load current
VD = catch diode forward voltage.
RL= output inductor series resistance.
This equation assumes maximum on resistance for the internal high side FET.
The lower limit is constrained by the minimum controllable on time which may be as high as 200 ns. The
approximate minimum output voltage for a given input voltage and minimum load current is given by:
VOUTMIN= 0.12x((VINMAX-IOMINx0.110)+VD)-(IOMINxRL)-VD        (14)
Where
VINMAX = maximum input voltage
IOMIN = minimum load current
VD = catch diode forward voltage.
RL= output inductor series resistance.
This equation assumes nominal on resistance for the high side FET and accounts for worst case variation of
operating frequency set point. Any design operating near the operational limits of the device should be
carefully checked to assure proper functionality.

Now,I want to konw how to get the formula 13 and 14,would you please do me a favor to give me detail calculation,not only the conclusion?

Thanks!