Hi,
I plan to synchronize the LP3906 with an external clock by SYNC pin with a 13MHz clock.
How many is frequency range and duty cycle necessary to external clock synchronization?
Best Regards,
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Hi,
I plan to synchronize the LP3906 with an external clock by SYNC pin with a 13MHz clock.
How many is frequency range and duty cycle necessary to external clock synchronization?
Best Regards,
Sheng-san
Thank you for your support.
We have begun to debug.
When D0 register is made 1 and it's changed to an external clock synchronous mode, output stops.
When it's changed to an external clock synchronous mode, is output halted?
Regards,
Kobayashi
Sheng-san,
1) How to generate Power On Reset ?
Even if we generate Power On Reset, all resister should be reset. This means, Clock is Internal mode.
What is VDD in datasheet page 23 ? VDD is AVDD ?
2) We used I2C enable resister instead of POR. Following is our sequence.
But we don’t success.
0mSec
Power On
Enable ENSW1 (pull up)
Disable ENSW2
Disable EN_T (GND)
------ Then SW1 is default voltage.
300mSec
Input External SYNC 13MKz +-5% Duty 50%+-6%
301mSec
I2C Setting
BKLDOEN 00100000 Disable
B1TV1 Set Voltage
B2TV1 Set Voltage
LDO1VCR Set Voltage
LDO2VCR Set Voltage
VCCR 00010001 B2GO and B1GO
SCR1 00101111 External Sync.
BKLDOEN 01110101 Enable
------ Then SW1 is stopped after disable.
302mSec
Enable: ENSW2, ENLDO1, ENLDO2
-----All output is almost zero volts.
3) Please let us know the example of sequence for external sync.
Thank you for your support.
Best Regards,
it's OK, No need to change these registers, B1GO and B2GO should not be matter for sync mode,
Xiaochen,
from the schematic of the chip, we believe the requirement is to have external 13MHz external clk level is same as AVDD and VINLDO12 pin. Did they ever successfully turn on the power rails with external 13MHz clk yet? what do you mean "sync.Mode control without EN_T"? from the datasheet, there is only one register to switch clk between internal 2MHz and ext 13MHz...