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LP3906 external clock synchronazation

Other Parts Discussed in Thread: LP3906

Hi,

I plan to synchronize the LP3906 with an external clock by SYNC pin with a 13MHz clock.

How many is frequency range and duty cycle necessary to external clock synchronization?

Best Regards,

  • I would say freq +/- 15%, and 50% duty cycle would be good enough..
  • Sheng-san

    Thank you for your support.

    We have begun to debug.

    When D0 register is made 1 and it's changed to an external clock synchronous mode, output stops.

    When it's changed to an external clock synchronous mode, is output halted?

    Regards,

    Kobayashi

  • did you change the register on fly? did you have the 13MHz clock available at SYNC pin when you changed the value? suggest to try change the register by I2C before enabling the device.
  • Sheng-san

    -did you change the register on fly?
    Yes

    -did you have the 13MHz clock available at SYNC pin when you changed the value?
    Yes

    -suggest to try change the register by I2C before enabling the device.
    Isn't it switched from internal clock to external clock synchronization dynamically?
    When changing a register, is it necessary to turn off output once and how long is time to turn off?

    Best Regards
    Kobayashi
  • I don't think this part was designed to take on fly clock changing. I guess the part need to go through POR (power-ON-Reset) in order to sync up w/ external 13MHz clock.
  • LP3906 Additional questions

    1) How to generate Power On Reset ?

    Even if we generate Power On Reset, all resister should be reset. This means, Clock is Internal mode.
    What is VDD in datasheet page 23 ? VDD is AVDD ?

    2) We used I2C enable resister instead of POR. Following is our sequence.
    But we don’t success.

    0mSec
    Power On
    Enable ENSW1 (pull up)
    Disable ENSW2
    Disable EN_T (GND)
    ------ Then SW1 is default voltage.
    300mSec
    Input External SYNC 13MKz +-5% Duty 50%+-6%

    301mSec
    I2C Setting
    BKLDOEN 00100000 Disable
    B1TV1 Set Voltage
    B2TV1 Set Voltage
    LDO1VCR Set Voltage
    LDO2VCR Set Voltage
    VCCR 00010001 B2GO and B1GO
    SCR1   00101111 External Sync.
    BKLDOEN 01110101 Enable

    ------ Then SW1 is stopped after disable.

    302mSec
    Enable: ENSW2, ENLDO1, ENLDO2

    -----All output is almost zero volts.

    3) Please let us know the example of sequence for external sync.

    Best Regards
    Akamastu
  • Sheng-san,

    1) How to generate Power On Reset ?      

    Even if we generate Power On Reset, all resister should be reset.  This means,  Clock is Internal mode.
    What is VDD in datasheet page 23 ?   VDD is AVDD ?

    2)   We used I2C enable resister instead of POR.  Following is our sequence.
    But we don’t success.

    0mSec
    Power On
       Enable ENSW1 (pull up)
       Disable ENSW2
       Disable EN_T  (GND)
               ------ Then SW1 is default voltage.
    300mSec
    Input External SYNC   13MKz +-5%  Duty 50%+-6%

    301mSec
    I2C Setting
    BKLDOEN  00100000   Disable
    B1TV1                  Set Voltage
    B2TV1                  Set Voltage
    LDO1VCR               Set Voltage
    LDO2VCR               Set Voltage
    VCCR      00010001    B2GO and B1GO
    SCR1      00101111    External Sync.
    BKLDOEN  01110101    Enable

              ------ Then SW1 is stopped after disable.

    302mSec
    Enable: ENSW2, ENLDO1, ENLDO2

              -----All output is almost zero volts.
                                                       
    3)  Please let us know the example of sequence for external sync.

    Thank you for your support.
    Best Regards,

  • What is the voltage level of your 13MHz clock? I do checked with Design today, and found out the level has to be same as VINLDO12 pin.
  • Sheng-san

    -Sync signal level is not I/O Electrical Characteristics ( Vil Max:0.4V, Vih Min:1.2V) in Page 9 ?
    Our Design is VINLDO12: 3.2~4.2V, SYNC clk: 3.0V Logic

    -Please answer or advice 1,2,3 on Jul 27, 2016 7:46 AM.


    Regards
  • Sheng-san

    We used a manual I2C setting to add a wait time between commands.
      1St Trial Internal clk mode
    BKLDOEN 00100000 Disable
    B1TV1 Set Voltage
    B2TV1 Set Voltage
    LDO1VCR Set Voltage
    LDO2VCR Set Voltage
    VCCR 00010001 B2GO and B1GO
    SCR1   00101110 Internal clk.
    BKLDOEN 01110101 Enable

    All outputs are OK.

    2nd Trial External clk mode
    BKLDOEN 00100000 Disable
    B1TV1 Set Voltage
    B2TV1 Set Voltage
    LDO1VCR Set Voltage
    LDO2VCR Set Voltage
    VCCR 00010001 B2GO and B1GO
    SCR1   00101111 External Sync.
    BKLDOEN 01110101 Enable

    BUCK1 was broken. ( Perhaps NFET was shorted.)

    Why ?
  • We have another question.

    We change to External sync mode, while B1GO and B2GO are 1.
    Is this OK?
    Do we need to change sync mode while B1GO and B2GG are 0 (Hold)?
  • it's OK, No need to change these registers, B1GO and B2GO should not be matter for sync mode, 

  • have you try to increase the 13MHz clock level to same as VINLDO12? when you did 2nd trial ext clk mode, were other outputs OK except BUCK1?
    the POR is generate by power cycle event (VINLDO12 pin). how many board did you try?
  • Sheng,

    customer's CLK input can support both TTL and CMOS. so should meet the chip requirements.

    The customer hopes to get an example of sync. Mode control without EN_T control.

    THanks!.
  • Xiaochen,

    from the schematic of the chip, we believe the requirement is to have external 13MHz external clk level is same as AVDD and VINLDO12 pin. Did they ever successfully turn on the power rails with external 13MHz clk yet? what do you mean "sync.Mode control without EN_T"? from the datasheet, there is only one register to switch clk between internal 2MHz and ext 13MHz...

  • Sheng,

    does that mean EN_T can be tied to high directly? then switch the internal regiser from INT sync to EXT SYNC?

    Customer would like to know if TI has an EVM setup and demonstrate a working EXT mode operation. This way, they can compare to TI's setting to theirs.

    Thanks!
  • Xiaochen,
    This is what I think how the part should operates, but need customer's feedback on their side, that's why I asked these questions in earlier reply. As we talked over the phone last week, this is a very old device, and original team is no longer with TI, unfortunately we don't have an EVM to verify in our lab.