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TP54319 failures

David Boyle1
Prodigy 150 points
Other Parts Discussed in Thread: TPS54319

We are seeing a high failure rate (40%) of the TPS54319 on the latest production run of one of our custom boards, after seeing no failures through several prototype runs.  The failure mode is a low impedance developing across the internal low side MOSFET (10 to 20 ohms) after just two or three power cycles of the device.  The failure effect is to create an additional bias load on VIN, but the TPS device otherwise appears to function normally.  All failed parts came from single lot number AEBI (note the "I" may be a "1", can't tell for sure).  

Despite the low power dissipation in the TPS, we speculated that the part was overheating due to poor solder bond at the thermal pad.  The thermal vias under the TPS were slightly enlarged by fab house and are likely thieving solder from thermal pad during reflow.   

To test the theory, we insulated the thermal pad and installed a new TPS device.  The part subsequently failed in the same manner within 2 power cycles.

So, we are concluding that the thermal pad solder bond is very critical on the device, and that the thermal vias must be reduced from the "as drilled" 18mils to "TI datasheet recommended" 12 mils.  Also, that the solder paste pattern should be maintained at 70% area coverage of pad, per TI datasheet.

To help us move forward with greater confidence, here are a few questions/requests for TI:

  1. Can you provide a sanity check on our findings?  
    1. Is it expected that the TPS would degrade in this manner so quickly with poor thermal bond at pad? 
    2. Can you explain how the part is being damaged (i.e., low side gate drive, low side body diode??)
  2. Can you confirm the TI via and solder paste recommendations shown in datasheet should be adequate to prevent the failure mode? 
    1. In particular, can solder paste pattern be a single centered pad (as we have now) or should it be implemented as an array of 4 smaller pads, per TI datasheet?  
    2. Also, should we stick with 5 thermal vias, per TI datasheet... or can we eliminate the center via to further reduce solder thieving?
  3. Can you confirm there are no known quality issues with lot number "AEBI"?
  4. Would it be possible to have TI perform failure analysis on a few failed devices, to confirm issue and resolution?

Thanks!

  • 0
    TI__Guru**** 191445 points
    I'll get someone to take a look at this next week. Can you post your schematic? There may be some other issue.
  • 0 in reply to JohnTucker
    Prodigy 150 points
    Ok, thanks. I don't see how to attach the schematic?
  • 0 in reply to JohnTucker
    Prodigy 150 points

    Hi John,

    I have not heard back from TI on this issue.  Is there anyway to get a dialogue with a TI engineer by email or phone?

    Thanks?

    DaveB

  • 0 in reply to David Boyle1
    TI__Guru**** 191445 points
    That part is supported out of or MCP team in China. If you email me at j(dash)tucker(at)ti(dot)com I can forward your request to my contacts on that team.

    The solder requirements are somewhat generic. They are from our packaging group and are tied to the package type, not the TPS54319 specifically. You may want to consult with you PCB assembler. They may have other recommendations specific for their process.

    I have not vetted this personally, but I suspect that vias from top side GND to back side copper GND plane directly adjacent to the IC rather than embedded into the thermal pad area would be nearly as effective for heat dissipation.

    I somewhat doubt that this is a thermal issue. TPS54319 has thermal shutdown protection that should inhibit long term operation above abs max junction temperature Usually when High side or low side FET is damaged, it is due to electrical overstress (typically over voltage transients. I suppose there could be something unique about your date code as well.