Hello,
We are designing a product that will include the TPS40170 and the LM5122 controllers. The TPS40170 will implement a 300kHz, 8~16V input, 5V, 30W output buck. The LM5122 will implement a 8~16V to 24V, 30W boost. If I want to synchronize the converters, to be able to run them at 300kHz, my idea is to use the SYNC output from the TPS40170 and the SYNCIN/RT input of the LM5122.
If I understand correctly, I will need to put the LM5122 in Master2 mode (OPT=VCC, FB=feedback), as shown in Table 1 of the datasheet. Also, figure 24 shows the connection of the syncrhonization signal via RT to the SYNCIN/RT pin.
Below figure 24, the datasheet says: "In master2 and slave modes, this external synchronization clock should be directly connected to the RT pin and always provided continuously".
However, just above figure 24, the datasheet says "With the configuration in Figure 24, the internal oscillator can be synchronized by connecting the external synchronization clock into the RT pin through RT resistor with free of the duty cycle limit. The output stage of the external clock source should be a low impedance totem-pole structure. Default logic state of fSYNC should be low."
This is really confusing. In my design, the TPS40170 will be running continuously, but the LM5122 will be turned on and off. What does the datasheet mean, when it says: "Default logic state of fSYNC should be low."?
Note: figure 33 shows a configuration in master2 mode, and also says "fSYNC should be always provided".
Note2: I see that I'll have to clamp the SYNC output of the TPS40170 from 7.5~8V to the 5Vpp needed.
Thank you very much for your help.
Best regards,
Diego.
