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TPS54550: Please teach me about TPS54550.

Part Number: TPS54550

Hi member.

I have gotten a question about TPS54550 from customer,now.

So, Could you teach me about TPS54550?

<Question>

If the SS / ENA terminal of this product is operated in the state of being pulled up with the PLD driven by 3.3 V,

if it is changed to the processing as described in the specifications, will it return to normal operation without device replacement Is it?

<Background>

I get a question this from customers,

"Is there a possibility of this product may be destroyed if it is operated in a state of being mistakenly Pulled Up SS/ENA Terminal to 3.3V Power ?"

· Customers understand that the SS / ENA terminal is controlled by Hi-Z or Low logic in the specification

· The customer used this devide that 3.3V drive PLD connected to the SS / ENA pin of this device

Best regards,

Masumi Sekiguchi

  • I'm not received the answer of this matter.
    Please answer me this matter.
  • Let me see what i can find out.  This part is somewhat older and the IC designer  is no longer with TI.  It may be next week before I can try it in the lab.

  • Thank you very much, John Tucker-san !!

    Is It likely that you will be able to experiment if it is next week?
    If the answe is"yes", please do it.

    And then…
    Here are the customer's updating comments which the following 2points.

    I'm glad for you if you answer about these.

    (Are there any missing conditions / information on confirming the following?)

    ① Operation to turn off the power before the power supply starts up
    It takes about 5 ms to turn on the power supply,
    but turn OFF ENA pin to LOW in the middle(at about 2 ms).

    Is there a problem with this behavior?

    ②Operation to turn on the power supply again before the power supply goes down

    When dropping the ENA pin to LOW and turning off the power,
    If the ENA pin was set to HiZ again before the output voltage dropped, the power supply did not start up sometimes.
    Does this case the IC to fail?
    Also, when turning on the power again after turning off the power that is there a condition specified?
    (Ex: power supply voltage needs to be lower than 〇〇V. etc.....)


    Could you help me?

    Best regards,
    Masumi Sekiguchi
  • Hi, John Tucker-san.
    How is this situation?

    Can it be measuring?

    Even if you can not measure, please contact to me this situation.
    Best regards.

    Masumi Sekiguchi
  • I will have to look to see if I have an EVM to check. If I have to order one it will be several days.

    Regards,
  • Hi, John Tucker-san.

    I acknowledged it.

    I will contact again you to look timing.
    Thank you very much.

    Masumi Sekiguchi
  • I checked an EVM. When SS/ENA is open, it is pulled up internally to 3 V. With an external supply tied directly to SS/ENA, when the supply is well below 3 V, SS/ENA sources 5 uA as it should. When SS/ENA is pulled above 3 V to 3.3 V, the supply sources about 1 uA back into the SS/ENA pin. This is all well below abs max and should cause no issue. Thee is an internal resistor in series with the SS/ENA. The internal pull down can pull the internal node down in a fault condition. This results in about 1.65 mA sink current still well below abs max. This devices is over 10 years old now and the IC designer has left TI.

    I do not have an easy way to test your sequencing conditions. I can tell you that TPS54550 is not designed to start into pre-bias. If you restart the device before the output discharges to zero, it will discharge when the low side FET turns on for the first time. It will stay on until the output discharges. This can possibly result in extremely large sink currents. When the low side turns off, the current must remain continuous and will go back to the input thru the high side body diode. This has been known to cause failures. You will have to carefully monitor your power cycling to avoid this.

    So while driving SS/ENA will not in and of itself cause failures, we recommend open drain drive.
  • Thank you very much for your enthusiastic support (measurement), John Tucker-san.
    Because I got the easily details of the explanation, I was able to do the explanation to the customer smoothly.

    By the way, please teach for customer in add.
    (But it may be dificulty to answer ....)

    Without replacing the IC temporarily controlled by the external power supply as it is,
    Is the IC already damaged when used back to recommended operation?

    Best regards,
    Masumi Sekiguchi
  • I am not sure about your follow up question. If you are concerned about restarting into a pre-bias, the failure mode would be a short from VIn to PH. That would be a catastrophic failure. If the TPS54550 restarts properly, then most likely it is not damaged. You would have to look at the sinking current. I have seen extreme cases where the current is > 60 A. In most cases it will be much less than that and no damage occurs.

    Let me know your circumstance. It has been many years since i last looked into this, but I may still have some presentation materials that I can share. I would have to search old back ups to find them.
  • I'm sorry for the late reply to you, John Tucker-san.

    I was able to talk with customers for the first time on this matter today.

    Customers understand that responsibility for this problem is themself,
    even if it answer is guess, he said he wanted to understand the mechanism.

    So, please let me know a little more.
    (We and TI don’t have to take responsibility from customers.)

    <Question>
    >If you restart the device before the output discharges to zero, it will discharge when >the low side FET turns on for the first time.
    >It will stay on until the output discharges.

    >This can possibly result in extremely large sink currents.
    >When the low side turns off, the current must remain continuous and will go back to >the input thru the high side body diode.
    >This has been known to cause failures.


    In this explanation, regardless of the processing of the "EN / SS" pin,
    As the same thing will occur if It have a charge to the output of this device is accumulated?

    Could you just tell us a little more about that?
    (I want to understand this phenomenon and answer to customers)
    (If I can answer it, this thread can be "CLOSED".)
  • It has been over ten years since I looked into this previously. I do not remember much about the details, only some general observations as outlined above. At the time I did generate some documentation on it. Let me see if I can find it. I think I am the only person left at TI who worked on that issue. It may take a few days to find it.
  • Thank you very much for your polite response.

    Since sending over a plurality of times is OK, too.
    So please send in order from what found.

    Best regards.

  • Hello.

    Sorry then you're busy,
    How is the situation in this case?

    Did you find the material?

    Please give feedback on the situation.
  • I took a brief search in my documents and did not find it. I may have it on a thumb drive. I'll look som more today.
  • Thank you for searching.
    If there is no material, will you comment me explain a little more about the contents below?
    Because it is necessary to explain the mechanism to the customer.

    So, I want to know about mechanism.

    >I can tell you that TPS54550 is not designed to start into pre-bias.
    >If you restart the device before the output discharges to zero,
    >it will discharge when the low side FET turns on for the first time.
    >It will stay on until the output discharges.
    >This can possibly result in extremely large sink currents.
    >When the low side turns off, the current must remain continuous and will go
    >back to the input thru the high side body diode.
    >This has been known to cause failures.
    >You will have to carefully monitor your power cycling to avoid this.


    Could you tell me about this?

  • If there is no material, will you comment me explain a little more about the contents below?
    Because it is necessary to explain the mechanism to the customer.

    So, I want to know about mechanism.

    >I can tell you that TPS54550 is not designed to start into pre-bias.
    >If you restart the device before the output discharges to zero,
    >it will discharge when the low side FET turns on for the first time.
    >It will stay on until the output discharges.
    >This can possibly result in extremely large sink currents.
    >When the low side turns off, the current must remain continuous and will go
    >back to the input thru the high side body diode.
    >This has been known to cause failures.
    >You will have to carefully monitor your power cycling to avoid this.


    Could you tell me about this?
  • Since I could not find the previous data, let me recount as best I can from memory.

    As stated above, When TPS54550 starts into a pre-bias condition, the feed back voltage is higher then the SS voltage (the non inverting error amp input is the lower of VREF and SS) so the low side FET is commanded on full time until the output is discharged enough for the feed back voltage to be slightly less than SS at which time the high side turns on. While the low side is originally on the inductor current is decreasing . It some instances with low value of L and high value of Cout, the inductor current can reach a very high negative value ( sinking current back to ground thru the low side FET). When the low side turns off, the inductor current must remain continuous and immediately conducts thru the high side body diode back into VIN. This may cause immediate high side FET damage for extremely high current or more likely charge the input capacitance locally (it may be a small value like 10 uF) up to a voltage above the abs max and cause EOS. In the case in question. This only occurred when the SS/ENA pin was toggled rapidly, I think in the range of 20 - 30 usec. Damaging currents were only observed in cases were a low value of Lout, higher output voltages such as 5 V or higher and large output capacitance. Large Vout and Cout means large energy storage and lower values of inductance allow the current to ramp faster.

    Unfortunately I do not have the exact details at hand, but this is the general case. You should ensure that you do not have any pre-bias voltage naturally occurring on the TPS54550 output form other system leakage paths. If you do have it make sure the pre-bias energy is not sufficient to cause negative currents grater than 10 to 12 A. Do not rapidly toggle SS/ENA. Allow enough time for the TPS54550 output to discharge. Under these conditions you should not have any reliability issues.