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LM25117-Q1: RT pin

kura
Genius 4680 points
Part Number: LM25117-Q1

Could you please advise us about following.

1.Please let us know RT coupling capacitor min,max value.

    We only found 100pf as a starting point at datasheet P15.

2.Please let us know RT Sync Negative Threshold value or Hysteresis if you have.

    We only found RT Sync Positive Threshold at datasheet P7.

    Does this part detect only rising edge of Sync signal?

  • 0
    TI__Mastermind 26450 points

    The Hysteresis on the Sync pin is 0.5V typically.

    The min value I recommend for the AC coupling cap on the sync pin is 100pF. I would keep the AC coupling capacitor within an order of magnitude of this value.

  • 0 in reply to David Baba
    Genius 4680 points

    David-san

    Thank you for your reply.

    (1)

    If you have more information about Hysteresis,please let us know min,max value of  Hysteresis on the Sync.

    (2)

    RT AC coupling capacitor

    I attached RT waveforms when we use coupling capacitpr 100pF or 390pF.

    Please check  attached and give us your comment.

    Regards,

    RT waveform.xlsx

  • 0 in reply to kura
    TI__Mastermind 26450 points

    The Synchronization is edge triggered and need only be 100ns in width as a minimum and need to be greater than 3.95V to guarantee a frequency "lock".  it is recommended to be within +/-10% of the RT set programming frequency. I would go with the 390pF coupling cap based on the waveforms you have provided to clear the 3.95V max threshold of the Sync input.

  • 0 in reply to David Baba
    Genius 4680 points

    David-san

    Thank you for your support.Please give us your advise more.

    We got RT waveforms at the case of coupling capacitor 100pF, 390pF,1000pF,2200pF,0.01uF.

    Please see attached.

    8475.RT waveform.xlsx

    (1)

    When UVLO is low, RT voltage become over Abs MAX.

    Please let us know Recommend Sequence of UVLO and RT.

    (2)

    If they use large coupling capaciitor,Term that RT voltage become stable is long.

    Is there any negative effect of using with  large coupling capaciitor?

    (3)

    Please let us know Min/Max value of RT hysterisis.(typ is 0.5V)

    Regards,

  • 0 in reply to kura
    TI__Mastermind 26450 points
    Hello,

    As previously mentioned I would use the 390pF to exceed the max threshold. If there is concern on the Absmax negative Switch, can use schottky from RT to Gnd to clamp negative voltage....(Kathode to RT Anode to Gnd).

    the 0.5V is typical, I do not have the max? However seeing as the closk signal is passing 0V on the input to the clock Sync, there will never be a violation of triggering Sync...
  • 0 in reply to David Baba
    TI__Expert 4365 points

    Here is a more explicit schematic of what David is recommending:

  • 0 in reply to Alan Martin
    Genius 4680 points

    Alan-san

     

    Thank you for your reply.

     

    Could you please let us know input timing information of RT pin and UVLO pin.

     

    If RT signal is before UVLO high, RT is over Abs MAX (<-0.3V).

  • 0 in reply to kura
    TI__Expert 4365 points
    I see in one of your last scope photos where there is the label UVLO(MCONT_ON) as a heading that there is evidence of input signal loading on the RT pin while the device is in shutdown. This is understandable because the oscillator section will be off until after the part is enabled. Please retake these waveforms with the lower Schottky diode installed and I'm sure the -0.3V sec will not be violated.
  • 0 in reply to Alan Martin
    Genius 4680 points

    Alan-san

    Thank you for your reply.

    Please check attached SW waveforms.

    <Conditions>

    Vin:16V

    Vout:8.6V

    Load:0.85A

    Sw frequency:320kHz

    waveforms.pptx

    If Load is SW continue on and off in Red circle in this file.

    Please let us know why this phenomenon was seen.(This phenomenon wasn't seen no load condition) and how to improve this.

    regards,

  • 0 in reply to kura
    TI__Mastermind 26450 points

    Referring to the unstable Switch node waveform.  Does this issue go away when the Sync pulse is disconnected? 

  • 0 in reply to David Baba
    Genius 4680 points
    Yes,this issue goes away when the Sync pulse is disconnected.
    Please let us know the reason why this phenomenon was seen ?
  • 0 in reply to kura
    TI__Mastermind 26450 points

    Please can you post the Vswitch malfunction with the waveform at the RT pin.  Please make sure you measure the RT waveform with a Short Gnd probe (kelvin connection) between RT and Gnd at the pins of the IC.

    Thank you.

  • 0 in reply to David Baba
    Genius 4680 points

    David-san

    Thank you for your reply.

    We got attached waveforms from customer.

    Please check attached.

    Regards,SW-RT.xlsx

  • 0 in reply to kura
    TI__Mastermind 26450 points

    Hello,

     

    I checked the waveforms and the RT waveforms look corrupt with noise to me?  there appears to be noise on the RT pin and its causing a false trigger of the clock.  How is the layout to of the Sync input?  The line of the Clock and Gnd return should be routed differentially to the IC?  Also you may want to try filtering the RT to Gnd with a small cap, perhaps this can help?

  • 0 in reply to David Baba
    Genius 4680 points

    David-san

    Thank you for your reply.

    When we get  customer answer for your question,we will post to E2E.

    By the way,

    LM25117QPSQX.xlsx

    1.They add diode to RT base on advise but costomer find RT pin voltage is over abs max. (pls see RT sheet)

     Please advise us how to prevent over  abs max.

    2..They find HO-SW,LO,RAMP voltage is over abs max. (pls see HO-SW_LO_RAMP sheet)

     Please advise us how to prevent over  abs max.

    Regards,

  • 0 in reply to kura
    TI__Mastermind 26450 points
    I did not see any waveforms on the RT Sheet?
    Regarding the negative voltage (-0.3V) where is this measured? needs to be right on pins with short ground probe and kelvin connected.
    Regarding the Ramp voltage, please can you provide schematic?

    Thanks.
  • 0 in reply to David Baba
    Genius 4680 points

    RT.xlsx

    David-san

    Thank you for your reply.

    1.RT waveform: attached

    You mentioned that "Also you may want to try filtering the RT to Gnd with a small cap, perhaps this can help?" in previous comment.

    If you have information reccomend a small cap value range ,please let us know it.

    2.Ramp voltage:When I get Circuit information from customer ,we will send it to you.

    3.Source of RT Noise may be SW ringing,if so,they think RGH/RGL value changing may be effective.

    If you have information of  acceptable range of RGH/RGL value,please let us know it.

    regards,

  • 0 in reply to kura
    TI__Mastermind 26450 points

    Hello,

     

    You may want to try a 47pF cap from RT to  Gnd at the RT pin, just to see if the instability goes away?

     

    If you believe the issue is caused by Vsw Ringing, then I suggest a top Gate resistor of ~5ohms or so.  I do not recommend placing a Rgate on the low side.

     

    You may also want to place an RC snubber across the Low side MOSFET.  Suggest  1Ohm and 100pF.

     

    Hope this helps?

     

    Kind regards,

     

    David Baba.

  • 0 in reply to David Baba
    Genius 4680 points

    David-san

    Regarding the Ramp voltage, I attache their schematic and give us your comment.

    Circuit.xlsx

    Please check attached.

  • 0 in reply to kura
    TI__Mastermind 26450 points
    Hello Kura san,

    I checked your schematic and I see that you have an input filter. If the input inductor has a low ESR<0.1ohm, this will need to be damped to avoid instability. You can dampen the filter by placing a capacitor in parallel with the existing Cin’s. Make sure this capacitor is ~5 x larger or more, greater than the Cin you current have, making sure it has an ESR of ~0.5 to 1ohm. Can you please try this and see if the issue resolves?


    Regarind the ramp circuit, please can you increase Rramp to ~100k.


    Hope this helps?

    Kind regards,

    David Baba.
  • 0 in reply to David Baba
    Genius 4680 points

    David-san

    Thank you veri much for your advise.

    They modified input circuit around RT pin.

    Coupling capacitor:0.022uF

    RT capacitor:82pF

    Sw waveform become good.

    But they still have problem that  RT pin voltage at start up is over -0.3V(abs MAX).

    I attache their RT circuit and waveform.Please give us your comment and let s know how to improve this waveform.

    Regards,RT circuit and waveform.xlsx

     

  • 0 in reply to kura
    TI__Mastermind 26450 points
    Hello Kura,

    Can you confirm what Diode they are using? Also is the Diode close to the RT and Gnd pin? And are they measuring the voltage accross the diode/Pins? thanks.

    Kind regards,

    David.
  • 0 in reply to David Baba
    Genius 4680 points

    David-san

    Diode is 1SS357.

    And they are measuring the voltage accross RT and DCDC_GND.

    We are asking the distance between Diode and RT to customer.

  • 0 in reply to kura
    Genius 4680 points
    David-san

    We got additional information.
    The distance between RT and Diode cathode is 3mm (2 layer board)
    The distance between AGND and Diode anode is 9.5mm.
    The distance between PGND and Diode anode is 9mm.
  • 0 in reply to kura
    TI__Mastermind 26450 points
    Hello Kura,



    The distance seems to be very far. Can you have them replace the Diode next to pins and re-measure?

    When they measure, the scope probe needs to be "kelvin" connected. Meaning a very short Ground lead. Use spring clip on barrel of the scope probe please.



    Thank you.
  • 0 in reply to David Baba
    Genius 4680 points

    Davis-san

    Thank you for your reply.

    Customer could replace the Diode next to pins and re-measure. Additional  wave form is attached.

    Diode cathode to RT pin distance：about 1mm

    Diode anode to GND pin distance：about 2mm

    Improvement is found but RT pin voltage at start up is still over -0.3V(abs MAX).

    Please give us your advise and any comment.

    RT circuit and waveform20170831.xlsx

  • 0 in reply to kura
    TI__Mastermind 26450 points
    Hello Kura san,

    I don’t think there is an issue; if a Schottky Diode placed by the pins is not conducting during start up I do not think an internal P-N parasitic junction will conduct either. I am not sure the measurements are real? If you have negative 1V on the anode of a schottky, the diode should conduct? Further, uou will have inductance on the pcb and pins of the device, have them re check measuring on the pins. Also have the customer place the Diode right by the device pins when they layout the board.

    Hope this helps?

    David.