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lm5002: external synchronization, what are the parameters

Leo Potjewijd
Prodigy 90 points
Part Number: LM5002

In optimizing the design at hand (externally synchronized boost converter) I ran into the puzzeling statement from the datasheet (page 9, paragraph 7.3.3) which states "The sync pulse width
measured at the RT pin must have a duration greater than 15 ns and less than 5% of the switching period".
In my case (frequency = 502kHz) this pulse would therefore need to be between 15 and 99 ns.

Based on the other information given in that same paragraph, I conclude that the time constant of the differentiating network formed by the timing resistor RT and the coupling capacitor must be roughly the same value.
Given the required RT of 24.9kΩ the time constant of the differentiating network, formed with the recommended 100pF coupling capacitor is 2.5ns 2.5us; which would mean this pulse will be way too short long...

What am I missing here?

  • 0
    TI__Mastermind 34201 points
    Hi Leo,

    When using LM5002 external synchronization function, the RT resistor will be superimposed by a AC pulse through the 100pF capacitor. The Peak voltage level should be greater than 2.6V to detect the sync signal.
    The RC differentiating network will create a high spike at the begging of each period for detection.

    Regards,
    Zack
  • 0 in reply to Zack Liu
    Prodigy 90 points
    Hi Zack,

    Best wishes for 2018.
    Sorry for the belayed response, I was caught up in all sorts of non-electronics stuff :(

    The high spike (as you call it) by the differentiating network is exactly the reason for my confusion: it follows the time-constant of that differentiating network (100pF/Rt= 24.9kΩ) which would result in a detect pulse duration of (roughly) 2.5us, given a square wave amplitude of 3.3Vpp. Please correct me if I'm mistaken here.

    The datasheet however calls for a duration between 15 and 5% of the switching period (5% of 1.99μs = 99.6 ns), so the resulting pulse would be 250 times(!) too long.
    Clearly there is something awry here, be it my understanding of differentiating networks or the datasheet...
  • 0 in reply to Leo Potjewijd
    TI__Mastermind 34201 points
    Hi Leo,

    Your understanding is correct.
    I use EVM and test it with a 1us pulse. The device can still work but I'd recommend you use a 15~99ns pulse if you want to use the external synchronization function.

    Regards,
    Zack
  • 0 in reply to Zack Liu
    Prodigy 90 points

    Thanks Zack,

    So, if I understand what you are saying correctly, I need a series capacitor of 3.3pF±20% to arrive at a pulse width within the stated 15-99ns (which is, btw, an awfully small range)? I defenitely NEED the external synchronization...
    It will take a fair amount of additional components to make that pulse over the full temperature range coming from 502kHz 50%DC, something I was hoping to avoid for space and cost reasons.

    But why do both the datasheet and WEBench then state 100pF if you need to calculate the value anyway (with no formulae or hints given)?

    Leo

  • 0 in reply to Leo Potjewijd
    TI__Mastermind 34201 points
    Hi Leo,

    3.3pF capacitor is too small.
    To meet the requirement about the sync pulse width on the RT pin, you need to change the external sync signal duty cycle.
    What's your external synchronization signal amplitude?

    Zack
  • 0 in reply to Zack Liu
    Prodigy 90 points

    Hi Zack,

    3.3pF is the value required with an RT of 24.9kΩ to get a tau of 82ns...

    The amplitude of the synchronizing signal is 3.3V with a duty-cycle of 50%; neither value can be changed without additional hardware, something we hope to avoid.

    That being said, there are also 1.2V and 5V circuits present in the design, one extra level converter may just be acceptable.

    Leo

  • 0 in reply to Leo Potjewijd
    TI__Mastermind 34201 points
    Leo,

    I used the evm and changed the capacitor to 10pF. It can not sync because with lower capacitance, the rising edge voltage will be smaller. If you use a 3.3V 50%DC signal, it can not get high enough rising edge voltage.
    Can you change the signal duty cycle less than 10%?
    What's the Vin, Vo, Io of your application? Maybe I can find another device for you.

    Regards,
    Zack
  • 0 in reply to Zack Liu
    Prodigy 90 points

    Zack,

    Thanks for the offer.

    The duty cycle can not be changed without extra circuitry: it is the output of a flipflop. The input to that flipflop (1MHz) is used to synchronize another switcher (buck to 5V) , which requires a minimum pulsewidth of 200ns and prefers 50% DC.
    In order to present a 50ns pulse to the LM5002 I would need to generate a 2MHz signal with 10%DC, run it through a flipflop to synchronize the buck regulator, add an RC network and AND gate to get a 1MHz signal with 5%DC, and run that through another flipflop/RCnetwork/AND gate to get the required 500kHz with 2.5%DC. All in all an undesirable increase of 7 (8 with decoupling) components, using single gate logic for space reasons...

    My Vi is between 7 oops: 6! and 27 Volts (nominal 13.2), Io is 80mA and Vo is 20 Volts. The Vo may rise to 27Volts, the circuit can handle that.
    The mentioned buck regulator needs to supply 600mA (load can vary between 20mA and 600mA) at 5V, with the same input conditions.
    Absolute paramount is synchronization with a whole multiple of 134.08kHz for both switchers; space is at a premium.

    Leo