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TPS53622: SVID transaction

user5070747
Prodigy 70 points
Part Number: TPS53622

Hello,

Have you ever seen the following ack(?) pulse from tps53622?

The details are as follows:

[environment]
Host : Intel Xeon
VR_0 (SVID addr 0) : another vendor's VR
VR_1 (SVID addr 1) : TI TPS53622

[issue]
This issue occurs every power-on sequence.
The pulse appears at the same timing.
At the moment, it seems that the pulse is from tps53622.
The reason is as follows:
 - the low-voltge-level is as same as tps53622. (not same as VR_0)
 - it does not appear, when tps53622 is disabled. (set svid addr 0xF by Fusion Digital Power Designer)

Is there anything for me to confirm?

Thanks,

  • 0
    TI__Expert 4060 points
    Hello,

    Happy to help, however can you please tell me a bit more about the problem so we can find root cause?

    1) Is the TPS53622 in a two phase or dual output configuration? Does this problem affect both rails if it's dual output?
    2) What is happening on the output of the regulator when this phantom data pulse appears? Does start up still occur and VOUT regulates properly or is it aborted?

    If you could share a schematic of your design and possibly get a scope capture of VOUT and PHASE during the phatom pulse we can work from there to dig deeper into the issue.

    Cheers,

    Carmen
  • 0 in reply to Carmen Parisi
    Prodigy 70 points

    Hi Carmen,

    Thank you for you reply.

    Please see my answers below:

    1) We use Dual-Channel (1-Phase + 1-Phase).
    This problem affect on SVID bus, but it seems that is not directly affect output rails.

    2) As a result, the system power-on sequence is failed, when  the phantom pulse apprears.
    We have not cleard up to which power-on steps have been proceeded normally.

    However, the SVID master maybe stop the power-on sequence.
    Because, when the phantom pulse appears, the SVID transaction seems to be sometimes garbled.
    Please see attached PDF.

    /cfs-file/__key/communityserver-discussions-components-files/196/svid_5F00_dbg_5F00_20180611a.pdf

    Have you ever seen similar issue, SVID garbled transaction?


    > If you could share a schematic of your design and possibly
    > get a scope capture of VOUT and PHASE during the phatom
    > pulse we can work from there to dig deeper into the issue.

    I will prepare for that.

    Thanks,

  • 0 in reply to user5070747
    TI__Expert 4060 points

    Hello,

    I can't say I've seen this exact issue before unfortunately but the SVID lines look like a good place to start debugging based on what you've shared.

    Can you confirm the pull-up resistor values allow for the rise times Intel calls out in their SVID spec documents? If they aren't sized correctly the trace capacitance will slow down the signal possibly causing the clock and data lines to become out of sync like you're seeing. Also, be sure to check the routing as well to make sure conforms to Intel's guidelines too.

    I can provide more insight as to whether or not the TPS53622 is the issue once you share the schematic and scope captures.

    Cheers,

    Carmen

  • 0 in reply to Carmen Parisi
    TI__Expert 4060 points
    Hello,

    Just checking to see if you can share your schematic and layout with me to review. After talking with some of the other apps engineers it may be an issue with your termination resistors or layout.

    I sent a friend request so we can exchange the data privately.

    Thanks,

    Carmen
  • 0 in reply to Carmen Parisi
    Prodigy 70 points

    Thank you for your cooperation.

    I have built  a environment to reproduce this issue.
    The environment are consist of one Pulse Generator (instead of Xeon) and one VR controller (TPS) only.
    At this time, the issue can reproduce on the environment, so I am evaluating this issue on that.

    I will contact you as soon as I know about the new result.

    Thanks,

  • 0 in reply to user5070747
    TI__Expert 4060 points
    Hello,

    Because two weeks have past since we last spoke I'd like to see if you had any new developments with this SVID issue? If it's resolved, excellent! Otherwise you can private message me the schematics for review as the layout and/or termination resistors are still the leading culprit.

    Cheers,

    Carmen
  • 0 in reply to Carmen Parisi
    Prodigy 70 points

    Sorry for late response.
    Unfortunately, this issue is not resolved yet.

    So, I have send you additional information - schematic data, layout data and a result on reproduce environment.

    If you hava any information, please let me know.

  • 0 in reply to user5070747
    TI__Expert 4060 points
    Hello,

    Thanks for the PM with your schematic and data collected so far. I answered you back in that channel.

    Cheers,

    Carmen