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TPS54610: Failure analysis is needed

Part Number: TPS54610

I have a quality claim from the customer on TPS54610MPWPREP. Mostly likely this is wrong schematics around than real defect inside. I need your verdict. 

Multiple failures were detected while monitoring TPS54610MPWPREP integrated circuits, which are a switching impulse (PWM) voltage regulator with integrated field effect transistors.

Table 1 – Information on batch TPS54610MPWPREP

Designation

IC labelling

Datacode

Q-ty of IC per batch

Number of failures

Batch No.

TPS54610MPWP*EP V62/05622-01XE V62/05622 TI

TPS54610EP

48.2016

512

 

264

9043427TW6

 

The following equipment and accessories were used for tests:

  1. Measuring complex for analog and digital-analog integrated circuits parameters DMT-219.
  2. Connecting device (CD) in the form of a board with built-in test panel for operative replacement of the tested samples TPS54610MPWPREP (E3 boards are shown in the figure 1)

Figure 1 – CD electrical schematic diagram and measuring instruments of DMT-219 complex for testing TPS54610MPWPREP

CD designed in full compliance with the typical layout of TPS54610MPWPREP, shown in Figure 10 page 9 of the technical description (datasheet) - see figure 2.

Figure 2 – Typical layout Figure 10 page 9 in the technical description TPS54610MPWPREP

When testing TPS54610MPWPREP batch the following functional and electrical parameters discrepancies of samples were detected with the technical description (datasheet):

  1. When checking SS/ENA terminal pin performance in ENABLE/DISABLE mode, an input voltage of 1.5V was applied to SS/ENA terminal pin causing an output voltage of up to 1.65V at a normal range of 3.3V. At the same time, the feedback voltage at the VSENSE pin was reduced to 0.5...0.6V, which is below the reference voltage (Vref = 0.891V). Test algorithm is shown in Fig. 3.

Figure 3 – TPS54610MPWPREP test oscillogram: 1) yellow graph – input voltage (VIN = 5V) – from the power source N6761AAgilent; 2) green graph – output voltage (Vo = 1.65V); 3) Purple graph - voltage on SS/ENA from power supply N6761AAgilent (Vena = 1.5V)

 

2. When checking SS/ENA terminal pin performance in ENABLE/DISABLE mode, an input voltage of 1.8V was applied to SS/ENA terminal pin causing an output voltage of up to 2.55V at a normal range of 3.3V. At the same time, the feedback voltage at the VSENSE pin was reduced to 0.6...0.7V, which is below the reference voltage (Vref = 0.891V). Test algorithm is shown in Fig. 4.

Figure 4 - TPS54610MPWPREP test oscillogram: 1) yellow graph – input voltage (VIN = 5V) – from the power source N6761AAgilent; 2) green graph – output voltage (Vo = 2.55V); 3) Purple graph - voltage on SS/ENA from power supply N6761AAgilent (Vena=1.8V)

 

3. When checking SS/ENA terminal pin performance in ENABLE/DISABLE mode, an input voltage of 3.3V was applied to SS/ENA terminal pin causing catastrophic failure of integrated circuit at a level of Vena≈3V. At the same time, there was a sharp increase in current consumption and, as a consequence, a decrease in the input voltage to a level of VIN = 2.9V. Test algorithm is shown in Figures 5 and 6.

Figure 5 – TPS54610MPWPREP test oscillogram: 1) yellow graph – input voltage (VIN = 5V) –from the power supply N6761AAgilent; 2) green graph – output voltage (Vo = 2.55V); 3) Violet graph – voltage on SS/ENA (Vena = 3.3V, current limit: 0.1mA)

 

Figure 6 – Increase in time sweep Figure 5

4. When checking the undervoltage protection performance (UVLO mode), SS/ENA output was switched to SS mode (power supply was disconnected from this output terminal), and the input voltage was applied alternately to IC of 2.8V and 5V, which led to UVLO protection circuit triggering. After 5-10 cycles of UVLO circuit triggering, some samples showed 3-fold or higher (45 mA and above) increase in current consumption, while maintaining all main integrated circuit features. Test algorithm is shown in Figures 7, 8, 9.

Figure 7 – TPS54610MPWPREP test oscillogram: 1) yellow graph – input voltage from the power supply N6761AAgilent; 2) green graph – output voltage (Vo=3.3V).

Figure 8 – Scaled mode check cycle of UVLO 7 performance in Figure 7

Figure 9 – Scaled mode check cycle of UVLO 7 performance in Figure 8

 

 

 

 

Test features:

1. N6761A Agilent power source was used for TPS54610MPWPREP power supply with current limitation of 25mA...100mA;

2. Various devices with different settings in accordance with the technical description (datasheet) were connected to SS/ENA input to check ENABLE/DISABLE mode in order to exclude the probability of device defect: 1) 2-quadrant precision power supply N6761AAgilent with current limitation of 10 mA; 2) 4-quadrant precision source-meter Keithley 2400 with current limitation of 10μA...500μA. In both cases, a catastrophic failure of TPS54610MPWPREP was observed, which eliminates the probability of defect in the master instrument (both instruments have passed the calibration by metrological services).

3. TPS54610MPWPREP IC was loaded on output using wire resistors at 3.3kΩ (equivalent load current – 1mA) and 33kΩ (equivalent load current – 0.1mA).

4. Fig. 10, shows for reference the voltage oscillograms from PH output (up to inductor)

Figure 10 – PH output voltage oscillograms

 

5. Test panel on the connecting device: TSSOP-28 4335 281 Loranger.

6. Cables for testing: coaxial with lengths up to 70 cm and high-frequency connectors (SMB, BNC).

Best regards,

Dmitry