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Looking at the datasheet where it talks about the feed-forward capacitor it seems to imply that the parallel combination of R1//R2 should be in the region of 150 kohm. However to achieve this would mean using something like 3.9 Mohms for R2 which seems too high to cope with the FB pin leakage current.
What would be the recommended values for R1, R2, Cff to achieve a 1.2 V output?
That wording for the Cff is for sizing the Cff based on the typical equivalent resistance of R1 and R2. It is not giving guidance on how to size R1 and R2.
For this IC, R2 should be kept less than 400k to keep the error from the FB leakage low. R1 is then sized according to equation 7 in the datasheet.
Regarding the Cff, it has 2 purposes--phase boost for the control loop and better operation in power save mode. With a 1.2V output and 1.153V reference, the phase boost that is possible to achieve is nearly 0. This is ok. So, the Cff should be sized to give best performance in power save mode. This should be done experimentally as it depends on the external L and Cout that are used, but 10 pF is a good starting point, per table 4.
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