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Q: TPS40021 Predictive gate delay by 1294176
I am looking over the datasheet for the TPS40021 and I have a question. On page 5 of the datasheet, it mentions the rise and fall times for the high side and low side drivers. There is no mention of the dead time between the turning off of the low side and turning on the high side as well as turning off the high side and turning on the low side. Do you know what this dead time is? I want to be sure that the FETs selected are not left on while the other is turning on.
I know that pg.10 of the datasheet talks about dead time, but there are no actual numbers. What is good design procedure for FET selection with predictive gate delay?
A: Re: TPS40021 Predictive gate delay by 10449
No dead times are provided for predictive gate drive because it varies with FET and operating conditions. The following two application notes can be found by searching on "predictive gate drive" from www.ti.com
The first application note provides a design example. In general, the MOSFET design proceedure does not change when using predictive gate drive. The overall converter performance is better with predictive gate drive than without it.
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