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Hi,

I've forwarded this to right engineer and he will answer early next week.

Thanks for your patience.

Hi,

nRESET_OUT = nRSTO;   nRESET_IN = nRSTI 

These are fairly standard notation use in the processor communities.

History of this may be routed back to the Intel and Marvell times long ago.

I think we (former NSC) could have make it more uniform.    And Chee Wooi Cheok

is right.  He caught an error on the "Power on Timing" table. 

t2 Delay from nBATT_FLT de-assertion to nRSTI assertion is NOT correct, on DS pg 53.

It should be:

t2 Delay from nBATT_FLT de-assertion to nRST0 assertion  ... typ 100 us.

The application intention was to facilitate end users to use a "push button" 

mechanism at the nRSTI input pin, which OR with several internal generated delayed

reset signals, manually forcing  an output reset at the nRSTO output pin.  nRSTO  issues

a hardware reset to the PXA and other apps processors as one convenient means to 

reboot a system when it gets "stuck" for some reason.

Hi Sheng Jin,

Thanks for replying.

Please refer to DS pg 53, it is stated in the reset sequence diagram that nRESET_OUT is from PXA27x Output.

In this case nRSTO from LP3972 is not equal to nRESET_OUT from PXA. Which signal is the waveform referrring to: nRTSO output from LP3972 or nRESET_OUT output from PXA??

Kindly enlighten.

Thanks & regards

Cheok

Any updates on the query?

nRTSO is not equal to nRESET_OUT as they are shown as 2 different waveform under LP3972 Reset Sequence on page 53.

Kindly enlighten

Thanks & regards

Cheok

Hi Chee Wooi Cheok,

As discussed in a previous thread the nRSTO signal may be generated by two mechanisms from the LP3972 PMU. One is fromthe native Power-On-Reset of the system/chip.  Another one  is a "forced" hardware reset signal initiated by some eletronic or mechanical means like a momentary  switch to generate a delayed reset signal to the processor. So either event could issue a nRSTO, which in turn issues to the PXA270 nRESET_IN pin.  The processor receives this reset signal from the PMU then it generates an appropriate system nRESET_OUT  signal with custom timing, level, etc. to other chips and sub-circuitsin the system.

[[ Reference relevant information From the PXA270 Data Sheet see below:

PXA270 nRESET_IN: This active-low, level-sensitive input starts the processor from the reset vector at address 0. Assertion causes the current instruction to terminate abnormally and causes a reset. When nRESET is driven high, the processor starts execution from address 0.nRESET must remain low until the power supply is stable. PXA270 V1.2 and higher: The nRESET_IN has a deglitch feature. That means, you have to pull the reset low for at least 35ms.

PXA270 nRESET_OUT: Reset Out: Asserted when nRESET is asserted, it deasserts after nRESET is deasserted but before the first instruction fetch occurs. nRESET_OUT is asserted during power-on, hardware, watchdog, and sleep-exit resets. It is configurable for GPIO reset. ]]

Hope this note answers your questions.

Regards,

Kern