I may have hit a slight problem with the power up/dn sequence of the TPS65217C (for AM335x with DDR3), even though it's the prescribed PMIC. It could just be an interpretation problem of the processor's datasheet. Do the dashed vertical lines in figures 4.1 to 4.5 (pages 91-95) of the processors198-page datasheet (SPRS717C) indicate a region where 1v8 and 1v5 can come up in either order? If so it could be better drawn, if not there's a problem as the PMIC's 1v5 DDR3 rail beats the 1v8 rail.
I have spotted several mentions of avoiding more than 2v difference between the ramping up/down of 1v8 and 3v3 regions, if this also applies to 1v5 & 1v8 then obviously it's met, but this isn't a stated requisite.
Using the TPS65217C with an Am335x and DDR3 we get:
Hope someone knows the answer?
The DDR3 rail and the 1.8V rail can come up at the same time. No specific requirement beyond that they both have to come up before the 3.3V rails.
We chose to stagger the DDR3 rail and the 1.8V rail by 1ms just simply so that we would have a known sequence.
The only real requirement is 1.5V/1.8V --> 3.3V --> VDD_CORE, VDD_MPU