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Maximum Inrush current expectations for TPS65070? Power up problem

Jeremy Huffman
Prodigy 80 points

Are there any maximum inrush current expectation for the TPS65070?  I am experiencing an occasional power up problem with this PMIC and am suspecting that it may be caused be excessive inrush current on the AC pin (the inrush appears to exceed 1A at power up).  There is no voltage applied to USB or BAT in my application.

When I observe the power up problem, I observe the output of the VDCDC2 to be at the voltage defined by the voltage divider at the DEFDCDC2 pin which is sourced by SYS (the divider resistors are 4.7kohm each).  When the PMIC powers up without problems and the OMAP processor boots, the VDCDC2 measures about 3.3V.  POWER_ON and PGOOD are logic low when I have the power up problem.  PB_OUT is about the same voltage as VDCDC2.

Given this, here are some questions to try and understand the power up problem:

*Is the PMIC possibly in low power mode or an odd state?

*What is causing the PGOOD and POWER_ON to be low?

*Is the OMAP expected to function and drive the POWER_ON high, even when it is only supplied by the ~2.3V to 2.7V I/O level?

*If there are inrush current expectations of the TPS65070 is there a way to set for that or adjust for it?

*When there is a power up problem and I have to manually drive the PB_IN low, does that provide a hint to where my problem lies?

  • 0
    TI__Genius 16870 points
    HI Jeremy,

    There is no expected in rush current that I know of. The PMU has soft-start that will significantly reduce this current by slowing the ramp rate of the DCDCs. The main contributing factor to inrush current is the caps so, check to see if they are similar to the datasheet specifications or the EVM.

    Otherwise, I think you should separate your load from the PMU to make sure this is not a load issue. If the load is shorted beyond the PMU's current capabilities then the PMU will not be able to regulate. Remove the load from the board and test solely the PMU.

    Also, measure the SW node and the FB pin to determine if the DCDC is at steady state or if it is still trying to ramp the VOUT.
  • 0 in reply to Michael Green
    Prodigy 80 points
    Thanks, Michael. I just edited my original post -- would you please reread it and adjust your reply. I know the problem is with my system -- the way my main system power supply is behaving with respect to the PMU.

    On one unit, one thing that I have discovered has helped reduce the frequency of the power up problems is by using the same supply (VDCDC2 output of PMU) to pull-up the OMAP's boot pins rather than another LDO that is separately powered from my system main supply, the one that supplies the PMU AC pin. Although on another unit with what I believe are tthe same changes, I still have the problem.
    It looks like PGOOD is always driven low for some reason.
    Somehow my OMAP is not booting up and I am not sure why that is.
    I have more debugging to do it seems.
  • 0 in reply to Jeremy Huffman
    TI__Genius 16870 points
    What could cause the PGOOD to be LOW? ...

    Try reading the x0B and x0C registers. They report the PGOOD statuses of each rail and allows you to select which rails to include in the PGOOD pin's generation. You can read which rail is not in regulation, mask it, then see if the PGOOD goes HIGH.