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TPS65910A3A VMMC is 4.2V!

Other Parts Discussed in Thread: AM3352

I have a design using a TPS65910A3A driving an Am3352. The voltage input to the TPS65910A3A is +5V. VAux33 and VAux2 are +3.3V as desired but VMMC is about +4.2V on powerup. When I push the reset button, it drops to +3.7V. Curiously, a previous design using the same TPS65910A3A circuit has the VMMC correct at +3.3V.

I see this on at least 3 boards and don't have any idea what is causing this as there is no voltage feedback loop to the PMIC.

Burt.

  • Does the rising slope of VMMC seem consistent to 4.2V, or does it jump at any particular time? If so, can we see if another higher voltage rail is enabling around this time that could be finding a path back to this node?
  • Hi Richard,

    +5V is connected to VCC3 which provides power for VMMC. +5V takes about 5.0msec to rise from 0V to 5.0V.

    VMMC starts to rise about 2.0msec after +5V starts to rise. VMMC plataeus at +1.6V when VCC3 reaches 5.0V (3.0msec later). VMMC stays at +1.6V for 2.0msec and then goes to +2.3V and stays there for about 8.0msec. VMMC then goes to +4.2V and stays there for 3.0 sec before dropping to +3.75V. VMMC stays at +3.75V.

    The only higher voltage rail is the +5.0V, which feeds all the PMIC voltage inputs, and it reaches +5.0V before VMMC goes to +4.2V.

    Burt.
  • Hi Burt,

    I'm assuming the +5V rail is shared still among all the other VCCx pins and likely tied to PWRHOLD, if this is incorrect please let me know. VMMC should not be enabled until about the 5th time slot, or about 10ms after the start-up reason. This means that the initial rise is either from an external regulator powered by the 5V rail, or coming from a previous rail in the PMIC like VDAC. Can you scope VDAC and VMMC simultaneously to determine if VDAC could be the initial source of the 1.6V? Given that the next jump is also about 2ms delayed, this could be another case of domain mixing. I'm not sure exactly how they could be adding together, but there could be 1.8V and 3.3V domains somehow tied together, either through peripherals or external pullups, and could be affecting your regulation on VMMC.
  • Hi Richard,

    Yes, the +5V rail is shared among the other VCCx pins. I've tried direct +5V connection to PWRHOLD and +5V through 11K resistor to PWRHOLD with no difference in behavior.

    I've mapped out the timing of the different voltage outputs of the PMIC:

    +5V: starts to rise at t0msec, reaches +5V at t5.0msec (5.0msec)

    VRTC: starts to rise at t3.5msec, reaches +1.8V at t5.5msec

    VDAC: starts to rise at t8.5msec, reaches +1.8V almost immediately (couple hundred usec)

    VDIG1, VDIG2: starts to rise at t10.0msec, reaches +1.8V almost immediately

    VAUX1, VPLL: starts to rise at t12.0msec, reaches +1.8v almost immediately

    VIO: starts to rise at T18.5msec, reaches +1.5V almost immediately, drops to 0.94V at t20.3msec

    VAUX2, VAUX33: starts to rise at t16.0msec, reaches +3.3V almost immediately

    VMMC: starts to rise at t2.0msec, reaches and stays at +1.5V at t5.0msec, rises to +2.3V at t7.0msec to t8.0msec and stays, rises to +4.2V at t16.0msec

    VDD1: starts to rise at t18.0msec, reaches +1.1V almost immediately

    VDD2: starts to rise at t20.0msec, reaches +1.1V almost immediately

    Only VMMC and VIO do NOT smoothly reach their final voltage levels. VMMC starts to rise even before VRTC. VMMC starts rise to +2.3V about 500usec before VDAC starts it's rise.

    Burt.

  • Hi Burt,

    The PMIC will not enable VMMC before VRTC, which points to this voltage likely being supplied by one of the connected loads. This can be confirmed by disconnecting VMMC from all loads and measuring on both sides of the break. VMMC should rise abruptly to 3.3V about 10mS after VDAC, and the loads should see voltages begin to appear well before VMMC is active. There is likely some other regulator or peripherals operating off the 5V rail that has a pull-up or internal connection to VMMC.

    I'm not sure if this will be directly related to the issue on VIO. According to the times listed, VIO starts to rise about the same time or after VDD1. VIO should begin rising earlier than this, at about 14ms according to the regulators. VIO also sees the voltage drop at 20ms, which is about the time the last core rail is enabled. Are you able to increase the current limit on VIO before the voltage drops to .94v?

  • Hi Richard,

    I have disconnected the PMIC VMMC output from the load. The PMIC VMMC output now provides only +3.3V. The load is just several VDDSHVx pins of an Am3352. Without a voltage regulator supplying power, those VDDSHVx pins go to +4.2V.

    VIO is still +0.94V.

    Burt.

  • Hi,

    I want to report that this issue is resolved.

    I had a 5V RS232 transceiver connected to the Am3352. This apparently fed back +4.2V to the CPU on its RXD line which raised the entire VDDSHV6 voltage rail. I changed to a +3.3V RS232 transceiver and VMMC and VDDSHV6 are normal at +3.3V.

    Burt.

  • Hi Burt that's great news!

    Did this affect the behavior of VIO as well?